 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| this is information on a product in full production. june 2016 docid027973 rev 4 1/115 stm32l011x3 stm32l011x4 access line ultra-low-power 32-bit mcu arm ? -based cortex ? -m0+, up to 16kb flash, 2kb sram, 512b eeprom, adc datasheet - production data features ? ultra-low-power platform ? 1.65 v to 3.6 v power supply ? - 40 to 125 c temperature range ? 0.23 a standby mode (2 wakeup pins) ? 0.29 a stop mode (16 wakeup lines) ? 0.54 a stop mode + rtc + 2 kb ram retention ? down to 76 a/mhz in run mode ? 5 s wakeup time (from flash memory) ? 41 a 12-bit adc conversion at 10 ksps ? core: arm ? 32-bit cortex ? -m0+ ? from 32 khz to 32 mhz max. ? 0.95 dmips/mhz ? reset and supply management ? ultra-safe, low-power bor (brownout reset) with 5 selectable thresholds ? ultralow power por/pdr ? programmable voltage detector (pvd) ? clock sources ? 0 to 32 mhz external clock ? 32 khz oscillator for rtc with calibration ? high speed internal 16 mhz factory-trimmed rc (+/- 1%) ? internal low-power 37 khz rc ? internal multispeed low-power 65 khz to 4.2 mhz rc ? pll for cpu clock ? pre-programmed bootloader ? usart, spi supported ? development support ? serial wire debug supported ? up to 28 fast i/os (23 i/os 5v tolerant) ? memories ? up to 16 kb flash memory with ecc ? 2 kb ram ? 512 b of data eeprom with ecc ? 20-byte backup register ? sector protection against r/w operation ? ? rich analog peripherals ? 12-bit adc 1.14 msps up to 10 channels (down to 1.65 v) ? 2x ultra-low-power comparators (window mode and wake up capability, down to 1.65 v) ? 5-channel dma controller, supporting adc, spi, i2c, usart, timers ? 4x peripherals communication interface ? 1x usart (iso 7816, irda), 1x uart (low power) ? 1x spi 16 mbits/s ? 1x i2c (smbus/pmbus) ? 7x timers: 1x 16-bit with up to 4 channels, 1x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x systick, 1x rtc and 2x watchdogs (independent/window) ? crc calculation unit, 96-bit unique id ? all packages are ecopack ? 2 table 1. device summary reference part number stm32l011x3 stm32l011g3, STM32L011K3, stm32l011e3, stm32l011f3, stm32l011d3 stm32l011x4 stm32l011g4, stm32l011k4, stm32l011e4, stm32l011f4, stm32l011d4 ufqfpn20 3x3 mm ufqfpn28 4x4 mm ufqfpn32 5x5 mm lqfp32 7x7 mm wlcsp25 2.133x2.070 mm tssop14/20 169 mils www.st.com
docid027973 rev 4 2/115 stm32l011x3/4 contents 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 arm? cortex?-m0+ core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.4 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 24 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11.1 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27 3.13 system configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14.1 general-purpose timers (tim2, tim21) . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14.2 low-power timer (lptim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14.3 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 contents stm32l011x3/4 3/115 docid027973 rev 4 3.15.1 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15.2 universal synchronous/asynchronous receiver transmitter (usart) . . 30 3.15.3 low-power universal asynchronous receiver transmitter (lpuart) . . . 31 3.15.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.16 cyclic redundancy check (crc) calculation unit . . . . . . . . . . . . . . . . . . . 31 3.17 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.2 embedded reset and power control bloc k characteristics . . . . . . . . . . . 49 6.3.3 embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.5 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.7 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.11 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.12 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.13 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.14 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.15 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 docid027973 rev 4 4/115 stm32l011x3/4 contents 4 6.3.16 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.17 comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.18 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.1 lqfp32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 ufqfpn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3 wlcsp25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.4 ufqfpn28 4 x 4 mm package information . . . . . . . . . . . . . . . . . . . . . . 101 7.5 ufqfpn20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6 tssop20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.7 tssop14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.8 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 7.8.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 list of tables stm32l011x3/4 5/115 docid027973 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. ultra-low-power stm32l011x3/x4 device features and peripheral counts. . . . . . . . . . . . . 11 table 3. functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15 table 4. cpu frequency range depending on dynamic voltag e scaling . . . . . . . . . . . . . . . . . . . . . . 16 table 5. functionalities depending on the working mode (from run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. stm32l011x3/4 peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. stm32l011x3/4 i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. spi implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 16. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 17. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 18. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 19. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 20. embedded internal reference voltage calibration valu es . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 21. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 table 22. current consumption in run mode, code with data processing running from flash. . . . . . 53 table 23. current consumption in run mode vs code type, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 24. current consumption in run mode, code wit h data processing running from ram . . . . . . 55 table 25. current consumption in run mode vs code type, code with data processing running from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 26. current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 27. current consumption in low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 28. current consumption in low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 29. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . . 59 table 30. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 60 table 31. average current consumption during wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 32. peripheral current consumption in run or sleep mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 33. peripheral current consumption in stop and stan dby mode . . . . . . . . . . . . . . . . . . . . . . . 62 table 34. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 35. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 36. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 37. lse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 38. 16 mhz hsi16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 39. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 40. msi oscillator ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 41. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 42. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 43. flash memory and dat a eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 44. flash memory and data eeprom endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 71 table 45. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 docid027973 rev 4 6/115 stm32l011x3/4 list of tables 6 table 46. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 47. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 48. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 49. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 50. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 51. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 52. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 53. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 54. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 55. r ain max for f adc = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 56. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 57. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 table 58. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 59. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 60. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 61. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 62. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 63. i2c frequency in all i2c modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 64. usart/lpuart characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 table 65. spi characteristics in voltage range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 66. spi characteristics in voltage range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 67. spi characteristics in voltage range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 68. lqfp32, 7 x 7 mm, 32-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 94 table 69. ufqfpn32, 5 x 5 mm, 32-pin package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 70. wlcsp25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 71. wlcsp25 recommended pcb design rules (0.4 mm pitc h) . . . . . . . . . . . . . . . . . . . . . . . 99 table 72. ufqpn28, 4 x 4 mm, 28-pin package mechanical da ta. . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 73. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 74. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 75. tssop14 ? 14-lead thin shrink sm all outline, 5.0 x 4.4 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 76. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 77. stm32l011x3/4 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 78. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 list of figures stm32l011x3/4 7/115 docid027973 rev 4 list of figures figure 1. stm32l011x3/4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 3. stm32l011x3/4 lqfp32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 4. stm32l011x3/4 ufqfpn32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 5. stm32l011x3/4 wlcsp25 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6. stm32l011x3/4 ufqfpn28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7. stm32l011x3/4 ufqfpn20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8. stm32l011x3/4 tssop20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. stm32l011x3/4 tssop14 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 11. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 13. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 14. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15. idd vs vdd, at ta= 25 c, run mode, code running from flash memory, range 2, 16 mhz hse, 1ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 16. idd vs vdd, at ta= 25 c, run mode, code running from flash memory, range 2, hsi16, 1ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 17. idd vs vdd, at ta= -40/25/ 55/ 85/105/125 c, low-power run mode, code running from ram, range 3, msi (range 0) at 64 khz, 0 ws . . . . . . . . . . . . . . . . . 58 figure 18. idd vs vdd, at ta= -40/25/55/ 85/105/125 c, stop mode with rtc enabled and running on lse low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 19. idd vs vdd, at ta= -40/25/55/85 /105/125 c, stop mode with rtc disabled, all clocks off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 20. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 21. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 22. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 23. hsi16 minimum and maximum value versus temperat ure . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 24. vih/vil versus vdd (cmos i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 figure 25. vih/vil versus vdd (ttl i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 26. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 27. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 28. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 29. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 30. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 31. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 32. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 33. lqfp32, 7 x 7 mm, 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 93 figure 34. lqfp32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 35. example of lqfp32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 36. ufqfpn32, 5 x 5 mm, 32-pin package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 37. ufqfpn32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 38. example of ufqfpn32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 39. wlcsp25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 40. wlcsp25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 41. example of wlcsp25 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 docid027973 rev 4 8/115 stm32l011x3/4 list of figures 8 figure 42. ufqpn28, 4 x 4 mm, 28-pin package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 43. ufqfpn28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 44. example of ufqfpn28 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 45. ufqfpn20 - 20-lead, 3x3 mm, 0.5 m m pitch, ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 46. ufqfpn20 - 20-lead, 3x3 mm, 0.5 m m pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 47. example of ufqfpn20 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 48. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 49. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 50. example of tssop20 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 51. tssop14 ? 14-lead thin shrink sm all outline, 5.0 x 4.4 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 52. example of tssop14 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 53. thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 introduction stm32l011x3/4 9/115 docid027973 rev 4 1 introduction the ultra-low-power stm32l011x3/4 family includes devices in 7 different package types from 14 to 32 pins. the description below gives an overview of the complete range of peripherals proposed in this family. these features make the ultra-low-power stm32l011x3/4 microcontrollers suitable for a wide range of applications: ? gas/water meters and industrial sensors ? healthcare and fitness equipment ? remote control and user interface ? pc peripherals, gaming, gps equipment ? alarm system, wired and wireless sensors, video intercom this stm32l011x3/4 datasheet should be read in conjunction with the stm32l0x1 reference manual (rm0377). for information on the arm ? cortex ? -m0+ core please refer to the cortex ? -m0+ technical reference manual, available from the www.arm.com website. figure 1 shows the general block diagram of the device family. docid027973 rev 4 10/115 stm32l011x3/4 description 32 2 description the access line ultra-low-power stm32l011x3/4 family incorporates the high-performance arm ? cortex ? -m0+ 32-bit risc core operating at a 32 mhz frequency, high-speed embedded memories (up to 16 kbytes of flash program memory, 512 bytes of data eeprom and 2 kbytes of ram) plus an extensiv e range of enh anced i/os an d peripherals. the stm32l011x3/4 devices provide high power efficiency for a wide range of performance. it is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes. the stm32l011x3/4 devices offer several analog features, one 12-bit adc with hardware oversampling, two ultra-low-power comparators, several timers, one low-power timer (lptim), three general-purpose 16-bit timers, one rtc and one systick which can be used as timebases. they also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock. moreover, the stm32l011x3/4 devices embed standard and advanced communication interfaces: one i2c, one spi, one usart, and a low-power uart (lpuart). the stm32l011x3/4 also include a real-time clo ck and a set of backup registers that remain powered in standby mode. the ultra-low-power stm32l011x3/4 devices operate from a 1.8 to 3.6 v power supply (down to 1.65 v at power down) with bor and from a 1.65 to 3.6 v power supply without bor option. they are available in the -40 to +125 c temperature range. a comprehensive set of power-saving modes allows the design of low-power applications. description stm32l011x3/4 11/115 docid027973 rev 4 2.1 device overview table 2. ultra-low-power stm32l011x3/x4 device features and peripheral counts peripheral stm32 l011d3 stm32 l011f3 stm32 l011e3 stm32 l011g3 stm32 l011k3 stm32 l011d4 stm32 l011f4 stm32 l011e4 stm32 l011g4 stm32 l011k4 flash (kbytes) 816 data eeprom (bytes) 512 ram (kbytes) 2 timers general- purpose 2 lptim 1 rtc/systick/iwdg/ wwdg 1/1/1/1 communi- cation interfaces spi 1 i 2 c 1 usart 1 lpuart 1 gpios 11 16 21 24 26/28 (1) 11 16 21 24 26/28 (1) clocks: hse (2) /lse/hsi/msi/lsi 1/1/1/1/1 12b synchronized adc number of channels 1 4 1 7/9 (3) 1 10 1 4 1 7/9 (3) 1 10 comparators 2 max. cpu frequency 32 mhz operating voltage 1.8 v to 3.6 v (down to 1.65 v at power-down) with bor option 1.65 v to 3.6 v without bor option operating temperatures ambient temperature: ?40 to +125 c junction temperature: ?40 to +130 c packages tssop 14 tssop/ ufqfpn 20 wlcsp 25 ufqfpn 28 lqfp/ ufqfpn 32 tssop 14 tssop/ ufqfpn 20 wlcsp 25 ufqfpn 28 lqfp/, ufqfpn 32 1. the devices feature 26 and 28 gpios on lqfp32 and ufqfpn32, respectively. 2. hse available only as exter nal clock input (hse bypass). 3. the devices feature 7 and 9 adc channels on ufqfpn20 and tssop20, respectively. docid027973 rev 4 12/115 stm32l011x3/4 description 32 figure 1. stm32l011x3/4 block diagram & 2 5 7 ( ; 0 & 3 8 ) p d [ 0 + ] 6 : ' 1 9 , & * 3 , 2 3 2 5 7 $ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & 7 h p s v h q v r u 5 ( 6 ( 7 & / . ) / $ 6 + ( ( 3 5 2 0 % 2 2 7 5 $ 0 ' 0 $ $ + % ) p d [ 0 + ] & 5 & % 5 , ' * ( $ 3 % ' % * ( ; 7 , $ ' & 6 3 , 7 , 0 & 2 0 3 / 6 ( % 5 , ' * ( $ 3 % , & 8 6 $ 5 7 / 3 8 $ 5 7 7 , 0 , : ' * 5 7 & : : ' * / 3 7 , 0 % & . 3 5 ( * + 6 ( + 6 , 0 3 / / 0 6 , / 6 , 3 0 8 5 ( * 8 / $ 7 2 5 9 ' ' 9 ' ' $ 9 5 ( ) b 2 8 7 1 5 6 7 3 9 ' b , 1 2 6 & b , 1 2 6 & b 2 8 7 & . b , 1 : . 8 3 [ 3 $ > @ 3 & > @ 3 % > @ $ , 1 [ 0 , 6 2 0 2 6 , 6 & . 1 6 6 f k , 1 3 , 1 0 2 8 7 , 1 , 1 ( 7 5 2 8 7 6 & / 6 ' $ 6 0 % $ 5 ; 7 ; 5 7 6 & 7 6 & . 5 ; 7 ; 5 7 6 & 7 6 f k 6 : ' 0 6 y 9 & 2 0 3 , 1 3 , 1 0 2 8 7 description stm32l011x3/4 13/115 docid027973 rev 4 2.2 ultra-low-power device continuum the ultra-low-power family offers a large choice of core and features, from 8-bit proprietary core up to arm ? cortex ? -m4, including arm ? cortex ? -m3 and arm ? cortex ? -m0+. the stm32lx series are the best choice to answer your needs in terms of ultra-low-power features. the stm32 ultra-low-power series are the best solution for applications such as gas/water meter, keyboard/mouse or fitness and healthcare application. several built-in features like lcd drivers, dual-bank memory, low-power run mode, o perational amplifiers, 128-bit aes, dac, crystal-less usb and many other definitely help you building a highly cost optimized application by reducing bom cost. stmicroelectronics, as a reliable and long-term manufacturer, ensures as much as possible pin-to -pin compatibility between all stm8lx and stm32lx on one hand, and between all stm32lx and stm32fx on the other hand. thanks to this un precedented scalability, your legacy applicat ion can be upgraded to respond to the latest market feature and efficiency requirements. docid027973 rev 4 14/115 stm32l011x3/4 functional overview 32 3 functional overview 3.1 low-power modes the ultra-low-power stm32l011x3/4 supports dynamic voltage scaling to optimize its power consumption in run mode. the voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system?s maximum operating frequency and the external voltage supply. there are three power consumption ranges: ? range 1 (v dd range limited to 1.71-3.6 v), with the cpu running at up to 32 mhz ? range 2 (full v dd range), with a maximum cpu frequency of 16 mhz ? range 3 (full v dd range), with a maximum cpu frequency limited to 4.2 mhz seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. sleep mode power consumption at 16 mhz is about 1 ma with all peripherals off. ? low-power run mode this mode is achieved with t he multispeed in ternal (msi) rc oscilla tor set to the low- speed clock (max 131 khz), execution from sram or flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. in low- power run mode, the clock frequency and the number of enabled peripherals are both limited. ? low-power sleep mode this mode is achieved by entering sleep mode with the internal voltage regulator in low-power mode to minimize the regulator?s operating current. in low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 khz. when wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. ? stop mode with rtc the stop mode achieves the lowest powe r consumption while retaining the ram and register contents and real time clock. all clocks in the v core domain are stopped, the pll, msi rc, hse and hsi rc oscillators are disabled. the lse or lsi is still running. the voltage regulator is in the low-power mode. some peripherals featuring wakeup capability can enable the hsi rc during stop mode to detect their wakeup condition. the device can be woken up from stop mode by any of the exti line, in 3.5 s, the processor can serve the interrupt or resume the code. the exti line source can be any gpio. it can be the pvd output, the comp arator 1 event or comparator 2 event functional overview stm32l011x3/4 15/115 docid027973 rev 4 (if internal reference voltage is on), it c an be the rtc alarm/tamper/timestamp/wakeup events, the usart/i2c/lpuart/lptim wakeup events. ? stop mode without rtc the stop mode achieves the lowest powe r consumption while retaining the ram and register contents. all clocks are stopped, the pll, msi rc, hsi and lsi rc, hse and lse crystal oscillator are disabled. some peripherals featuring wakeup capability can enable the hsi rc during stop mode to detect their wakeup condition. the voltage regulator is in the low-power mode. the device can be woken up from stop mode by any of the exti line, in 3.5 s, the processor can serve the interrupt or resume the code. the exti line source can be any gpio. it can be the pvd output, the comparator 1 event or comparator 2 event (if internal reference voltage is on). it can also be wakened by the usart/i2c/lpuart/lptim wakeup events. ? standby mode with rtc the standby mode is used to achieve the lowest power consumption and real time clock. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hse bypass and hsi rc oscillators are also switched off. the lse or lsi is still running. after entering standby mode, the ram and register contents are lost except fo r registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz os cillator, rcc_csr register). the device exits standby mode in 60 s when an external reset (nrst pin), an iwdg reset, a rising edge on one of the three wkup pins, rtc alarm (alarm a or alarm b), rtc tamper event, rtc timestamp event or rtc wakeup event occurs. ? standby mode without rtc the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hsi and lsi rc, hse and lse cr ystal oscillator are also switched off. after entering standby mode, the ram and register contents are lost except for registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz oscillator, rcc_csr register). the device exits standby mode in 60 s when an external reset (nrst pin) or a rising edge on one of the three wkup pin occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped automatically by entering stop or standby mode. table 3. functionalities depending on the operating power supply range operating power supply range functionalities depending on the operating power supply range adc operation dynamic voltage scaling range i/o operation v dd = 1.65 to 1.71 v adc only, conversion time up to 570 ksps range 2 or range 3 degraded speed performance v dd = 1.71 to 1.8 v (1) adc only, conversion time up to 1.14 msps range 1, range 2 or range 3 degraded speed performance docid027973 rev 4 16/115 stm32l011x3/4 functional overview 32 v dd = 1.8 to 2.0 v (1) conversion time up to 1.14 msps range1, range 2 or range 3 degraded speed performance v dd = 2.0 to 2.4 v conversion time up to 1.14 msps range 1, range 2 or range 3 full speed operation v dd = 2.4 to 3.6 v conversion time up to 1.14 msps range 1, range 2 or range 3 full speed operation 1. cpu frequency changes from initial to final must respect the condition: f cpu initial <4f cpu initial . it must also respect 5 s delay between two changes. for example to switch from 4.2 mhz to 32 mhz, you can switch from 4.2 mhz to 16 mhz, wait 5 s, then switch from 16 mhz to 32 mhz. table 4. cpu frequency range de pending on dynamic voltage scaling cpu frequency range dynamic voltage scaling range 16 mhz to 32 mhz (1ws) 32 khz to 16 mhz (0ws) range 1 8 mhz to 16 mhz (1ws) 32 khz to 8 mhz (0ws) range 2 32 khz to 4.2 mhz (0ws) range 3 table 3. functionalities depending on the operating power supply range (continued) operating power supply range functionalities depending on the operating power supply range adc operation dynamic voltage scaling range i/o operation table 5. functionalities depending on the working mode (from run/active down to standby) (1)(2) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability cpu y - y - - - - - flash memory o o o o - - - - ram y y y y y - - - backup registers y y y y y - y - eeprom o o o o - - - - brown-out reset (bor) oooooooo dma o o o o - - - - functional overview stm32l011x3/4 17/115 docid027973 rev 4 programmable voltage detector (pvd) oooooo-- power-on/down reset (por/pdr) yyyyyyyy high speed internal (hsi) oo-- (3) --- high speed external (hse) oooo---- low speed internal (lsi) ooooo-o- low speed external (lse) ooooo-o- multi-speed internal (msi) ooyy---- inter-connect controller yyyyy--- rtc o o o o o o o - rtc tamper o o o o o o o o auto wakeup (awu) ooooo-oo usart o o o o o (4) o- - lpuart o o o o o (4) o- - spi o o o o - - - i2c o o o o o (5) o- - adc o o - - - - - - temperature sensor ooooo--- comparators o o o o o o - - 16-bit timers o o o o - - - - lptim o o o o o o - - iwdg o o o o o o o o wwdg o o o o - - - - systick timer o o o o - - - - gpios o o o o o o - 2 pins table 5. functionalities depending on the working mode (from run/active down to standby) (continued) (1)(2) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability docid027973 rev 4 18/115 stm32l011x3/4 functional overview 32 3.2 interconnect matrix several peripherals are directly interconnec ted. this allows autonomous communication between peripherals, thus saving cpu resources and power consumption. in addition, these hardware connections allow fast and predictable latency. depending on peripherals, these interconnect ions can operate in run, sleep, low-power run, low-power sleep and stop modes. wakeup time to run mode 0 s 6 cpu cycles 3 s 7 cpu cycles 5s 65s consumption v dd =1.8 to 3.6 v (typ) down to 128 a/mhz (from flash) down to 31 a/mhz (from flash) down to 7a down to 3.8 a 0.29 a (no rtc) v dd =1.8 v 0.18 a (no rtc) v dd =1.8 v 0.54 a (with rtc) v dd =1.8 v 0.41 a (with rtc) v dd =1.8 v 0.34 a (no rtc) v dd =3.0 v 0.23 a (no rtc) v dd =3.0 v 0.67 a (with rtc) v dd =3.0 v 0.53 a (with rtc) v dd =3.0 v 1. legend: ?y? = yes (enable). ?o? = optional, can be enabled/disabled by software) ?-? = not available 2. the consumption values given in this ta ble are preliminary data given for indicati on. they are subject to slight changes. 3. some peripherals with wakeup from stop capability can reques t hsi to be enabled. in this case, hsi is woken up by the peripheral, and only feeds the peripheral which requested it. hsi is automatically put off when the peripheral does not need it anymore. 4. uart and lpuart reception is functional in stop mode. it generates a wakeup interrupt on start.to generate a wakeup on address match or received frame event, the lpuart can run on lse clock while the uart has to wake up or keep running the hsi clock. 5. i2c address detection is functional in stop mode. it generates a wakeup interrupt in case of address match. it will wake up the hsi during recepti on. table 5. functionalities depending on the working mode (from run/active down to standby) (continued) (1)(2) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability table 6. stm32l011x3/4 peripherals interconnect matrix interconnect source interconnect destination interconnect action run sleep low- power run low- power sleep stop compx tim2,tim21 timer input channel, trigger from analog signals comparison yy y y - lptim1 timer input channel, trigger from analog signals comparison yy y y y functional overview stm32l011x3/4 19/115 docid027973 rev 4 3.3 arm ? cortex ? -m0+ core the cortex-m0+ processor is an entry-level 32-bit arm cortex processor designed for a broad range of embedded applications. it offers significant benefits to developers, including: ? a simple architecture that is easy to learn and program ? ultra-low power, energy-efficient operation ? excellent code density ? deterministic, high-performance interrupt handling ? upward compatibility with co rtex-m processor family ? platform security robustness. the cortex-m0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage pipeline von neumann architecture. the processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. the cortex-m0+ processor provides the except ional performance expected of a modern 32- bit architecture, with a higher code density t han other 8-bit and 16-bit microcontrollers. owing to its embedded arm core, the stm32l 011x3/4 are compatible with all arm tools and software. timx timx timer triggered by other timer yy y y - rtc tim21 timer triggered by auto wake-up yy y y - lptim1 timer triggered by rtc event yy y y y all clock source timx clock source used as input channel for rc measurement and trimming yy y y - gpio timx timer input channel and trigger yy y y - lptim1 timer input channel and trigger yy y y y adc conversion trigger y y y y - table 6. stm32l011x3/4 peripherals interconnect matrix (continued) interconnect source interconnect destination interconnect action run sleep low- power run low- power sleep stop docid027973 rev 4 20/115 stm32l011x3/4 functional overview 32 nested vectored interrupt controller (nvic) the ultra-low-power stm32l011x3/4 embed a nes ted vectored interrupt controller able to handle up to 32 maskable interrupt channels and 4 priority levels. the cortex-m0+ processor closely integrates a configurable nested vectored interrupt controller (nvic), to deliver industry-leading interrupt performance. the nvic: ? includes a non-mask able interrupt (nmi) ? provides zero jitte r interrupt option ? provides four interr upt priority levels the tight integration of the processor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing the interrupt latency. this is achieved through the hardware stacking of registers, and the abilit y to abandon and restart load- multiple and store-multiple operations. interrupt handlers do not require any assembler wrapper code, removing any code overhead from the isrs. tail-chaining optimization also significantly reduces the overhead when switching from one isr to another. to optimize low-power designs, the nvic int egrates with the sleep modes, that include a deep sleep function that enables the entire device to enter rapidly stop or standby mode. this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.4 reset and supply management 3.4.1 power supply schemes ? v dd = 1.65 to 3.6 v: external power supply fo r i/os and the internal regulator. provided externally through v dd pins. ? v ssa , v dda = 1.65 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. on tssop14 package, v dda is internally connected to v dd . 3.4.2 power supply supervisor the devices feature an integr ated zeropower power-on reset (por)/power-down reset (pdr) that can be coupled with a brownout reset (bor) circuitry. two versions are available: ? the version with bor activated at power-on operates between 1.8 v and 3.6 v. ? the other version without bor oper ates between 1.65 v and 3.6 v. after the v dd threshold is reached (1.65 v or 1.8 v depending on the bor which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the bor permanently: in this case, the vdd min value becomes 1.65 v (whatever the version, bo r active or not, at power-on). when bor is active at power- on, it ensures proper operation starting from 1.8 v whatever the power ramp-up phase before it reaches 1.8 v. when bor is not active at power-up, the power ramp-up should guarantee that 1.65 v is reached on v dd at least 1 ms after it exits the por area. functional overview stm32l011x3/4 21/115 docid027973 rev 4 five bor thresholds are available through opti on bytes, starting from 1.8 v to 3 v. to reduce the power consumption in stop mode, it is possible to automatically switch off the internal reference voltage (v refint ) in stop mode. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. note: the start-up time at power-on is typically 3.3 ms when bor is active at power-up, the start- up time at power-on can be decreased down to 1 ms typically for devices with bor inactive at power-up. the devices feature an embedded programmable voltage detector (pvd) that monitors the v dd/vdda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd/vdda drops below the v pvd threshold and/or when v dd/vdda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.4.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. ? mr is used in run mode (nominal regulation) ? lpr is used in the low-power run, low-power sleep and stop modes ? power down is used in standby mode. the regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and ram are lost except for the st andby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz oscillator, rcc_csr). 3.4.4 boot modes at startup, boot0 pin and nboot0, nboot1 and nboot_sel option bits are used to select one of three boot options: ? boot from flash memory ? boot from system memory ? boot from embedded ram the boot loader is located in system memory. it is used to reprogram the flash memory by using spi1 (pa4, pa7, pa13 and pa14 on tsso p14 package or pa4, pa5, pa6 and pa7 on other packages) or usart2 (pa2, pa3 and pa9, pa10). see stm32? microcontroller system memory boot mode an2606 for details. docid027973 rev 4 22/115 stm32l011x3/4 functional overview 32 3.5 clock management the clock controller distributes the clocks coming from different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. it features: ? clock prescaler to get the best trade-off between speed a nd current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. ? safe clock switching clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? system clock source three different clock sources can be used to drive the master clock sysclk: ? 0-32 mhz high-speed external (hse bypass), that can supply a pll ? 16 mhz high-speed internal rc oscillator (h si), trimmable by software, that can supply a pll ? multispeed internal rc oscilla tor (msi), trimmable by soft ware, able to generate 7 frequencies (65 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.1 mhz, 4.2 mhz). when a 32.768 khz clock source is available in the system (lse), the msi frequency can be trimmed by software down to a 0.5% accuracy. ? auxiliary clock source two ultra-low-power clock sources that c an be used to drive the real-time clock: ? 32.768 khz low-speed external crystal (lse) ? 37 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock can be measured using the high-speed internal rc oscillator for greater precision. ? rtc clock sources the lsi, lse or hse sources can be chosen to clock the rtc, whatever the system clock. ? startup clock after reset, the microcontroller restarts by default with an internal 2 mhz clock (msi). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css) this feature can be enabled by software. if an lse clock failure occurs, it provides an interrupt or wakeup event which is generated assuming it has been previously enabled. this feature is not available on the hse clock. ? clock-out capability (mco: microcontroller clock output) it outputs one of the internal clocks for external use by the application. several prescalers allow the configuration of the ahb fr equency, each apb (apb1 and apb2) domains. the maximum frequency of the ahb and the apb domains is 32 mhz. see figure 2 for details on the clock tree. functional overview stm32l011x3/4 23/115 docid027973 rev 4 figure 2. clock tree 0 6 y 9 / h j h q g + 6 ( + l j k v s h h g h [ w h u q d o f o r f n v l j q d o + 6 , + l j k v s h h g l q w h u q d o f o r f n v l j q d o / 6 , / r z v s h h g l q w h u q d o f o r f n v l j q d o / 6 ( / r z v s h h g h [ w h u q d o f o r f n v l j q d o 0 6 , 0 x o w l v s h h g l q w h u q d o f o r f n v l j q d o : d w f k g r j / 6 / 6 , 5 & / 6 ( 2 6 & 5 7 & / 6 , w h p s r # 9 + 6 , 5 & / h y h o v k l i w h u v + 6 ( % < 3 $ 6 6 / h y h o v k l i w h u v / 6 ( w h p s r 0 6 , 5 & / h y h o v k l i w h u v / h y h o v k l i w h u v 3 / / ; $ + % 3 5 ( 6 & ? & o r f n 6 r x u f h & r q w u r o # 9 # 9 # 9 # 9 # 9 # 9 # 9 , & & / . / 3 8 $ 5 7 8 $ 5 7 & / . / 3 7 , 0 & / . / 6 ( + 6 , 6 < 6 & / . 3 & / . / 6 , q r w v o h h s r u g h h s v o h h s q r w v o h h s r u g h h s v o h h s q r w g h h s v o h h s q r w g h h s v o h h s + & / . 7 , 0 [ & / . & . b 3 : 5 ) & / . 3 / / & / . + 6 ( + 6 , 0 6 , / 6 ( / 6 , # 9 # 9 ' ' & 2 5 ( f n b u f k v + 6 , 0 6 , 0 + ] f n b s o o l q ( q d e o h : d w f k g r j 5 7 & h q d e o h $ ' & h q d e o h $ ' & & / . / 6 8 / 6 ' / 6 ' 0 & 2 0 & 2 6 ( / 3 / / 6 5 & 5 7 & 6 ( / 6 \ v w h p & o r f n 3 h u l s k h u d o v h q d e o h 3 h u l s k h u d o v h q d e o h 3 h u l s k h u d o f o r f n h q d e o h 3 & / . w r $ 3 % s h u l s k h u d o v , i $ 3 % s u h v f [ h o v h [ w r 7 , 0 3 h u l s k h u d o f o r f n h q d e o h $ 3 % 3 5 ( 6 & 3 h u l s k h u d o f o r f n h q d e o h 3 & / . w r $ 3 % s h u l s k h u d o v 0 + ] p d [ , i $ 3 % s u h v f [ h o v h [ w r 7 , 0 3 h u l s k h u d o v h q d e o h $ 3 % 3 5 ( 6 & docid027973 rev 4 24/115 stm32l011x3/4 functional overview 32 3.6 low-power real-time cl ock and backup registers the real time clock (rtc) and the 5 backup registers are supplied in all modes including standby mode. the backup registers are five 32-b it registers used to store 20 bytes of user application data. they are not reset by a system reset, or when the device wakes up from standby mode. the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format ? automatically correction for 28, 29 (leap year), 30, and 31 day of the month ? two programmable alarms with wake up from stop and stan dby mode capability ? periodic wakeup from stop and standby with programmable resolution and period ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy ? 2 anti-tamper detection pins with programma ble filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 37 khz) ? the high-speed external clock 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated alternate function regi sters. all gpios are high current capable. each gpio output, speed can be slowed (40 m hz, 10 mhz, 2 mhz, 400 khz). the alternate function configuration of i/os can be locked if needed following a specific sequence in order to avoid spurious writing to the i/o registers. the i/o controller is connected to a dedicated io bus with a toggling speed of up to 32 mhz. the boot0 pin is shared with pb9 gpio pin. this pin is an input-only pin. if nboot_sel option bit is reset, sampling this pin on nrst rising edge gives the internal boot0 state. this pin then works as pb9 pin. the input volta ge characteristics of this pin are specific for boot0 pin type (see table 50: i/o static characteristics ). extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 26 edge det ector lines used to generate interrupt/event requests. each line can be individually configured to select the trigger event functional overview stm32l011x3/4 25/115 docid027973 rev 4 (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the in ternal apb2 clock period. up to 38 gpios can be connected to the 16 configurable interr upt/event lines. the 10 other lines are connected to pvd, rtc, usart, i2c, lpuart, lptim or comparator events. 3.8 memories the stm32l011x3/4 devices have the following features: ? 2 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. with the enhanced bus matrix, op erating the ram does not lead to any performance penalty during accesses to th e system bus (ahb and apb buses). ? the non-volatile memory is divided into three arrays: ? 8 or 16 kbytes of embedded flash program memory ? 512 bytes of data eeprom ? information block containing 32 user and factory options bytes plus 4 kbytes of system memory the user options bytes are used to write-pr otect or read-out protect the memory (with 4 kbyte granularity) and/or readout-protect the whole memory with the following options: ? level 0 : no protection ? level 1 : memory readout protected. the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2 : chip readout protected, debug features (cortex-m0+ serial wire) and boot in ram selection disabled (debugline fuse) the whole non-volatile memory embeds th e error correction code (ecc) feature. 3.9 direct memory access (dma) the flexible 5-channel, general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, lpuart, general-purpose timers, and adc. docid027973 rev 4 26/115 stm32l011x3/4 functional overview 32 3.10 analog-to-digita l converter (adc) a native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital converter is embedded into stm32l011x3/4 devices. it has up to 10 external channels and 2 internal channels (temperature sensor, volt age reference). three channels, pa0, pa4 and pa5, are fast channels, while the others are standard channels. the adc performs conversions in single-shot or scan mode. in sc an mode, automatic conversion is performed on a selected group of analog inputs. the adc frequency is independent from t he cpu frequency, allo wing maximum sampling rate of 1.14 msps even with a low cpu spee d. the adc consumption is low at all frequencies (~25 a at 10 ksps, ~200 a at 1msps). an auto-shutdown function guarantees that the adc is powered off ex cept during the active conversion phase. the adc can be served by the dma controller. it can operate from a supply voltage down to 1.65 v. the adc features a hardware oversampler up to 256 samples, this improves the resolution to 16 bits (see an2668). an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all scanned channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) can be internally connected to the adc start triggers, to allow the application to synchronize a/d conversions and timers. 3.11 temperature sensor the temperature sensor (t sense ) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in18 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode (see table 57: temperature sensor calibration values ). 3.11.1 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally con nected to the adc_in17 input channel. it enables accurate monitoring of the v dd value (since no external voltage, v ref+ , is available for adc). the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area (see table 20: embedded internal reference voltage calibration values ). it is accessible in read-only mode. functional overview stm32l011x3/4 27/115 docid027973 rev 4 3.12 ultra-low-power comparators and reference voltage the stm32l011x3/4 embed two comparators sharing the same current bias and reference voltage. the reference voltage can be internal or external (coming from an i/o). ? one comparator with ultra low consumption ? one comparator with rail-to-rail inputs, fast or slow mode. ? the threshold can be one of the following: ? external i/o pins ? internal reference voltage (v refint ) ? submultiple of internal reference voltage(1/4, 1/2, 3/4) for the rail to rail comparator. both comparators can wake up the devices from stop mode, and be combined into a window comparator. the internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 a typical). 3.13 system config uration controller the system configuration cont roller provides the capabilit y to remap some alternate functions on different i/o ports. the highly flexible routing inte rface allows the application firm ware to control the routing of different i/os to the tim2, tim21 and lptim1 timer input captures. it also controls the routing of internal analog signals to th e adc, comp1 and comp2 and the internal reference voltage v refint . 3.14 timers and watchdogs the ultra-low-power stm32l011x3/4 devices include two general-purpose timers, one low- power timer (lptim1), two watchdog timers and the systick timer. table 7 compares the features of the general-purpose and basic timers. table 7. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim2 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim21 16-bit up, down, up/down any integer between 1 and 65536 no 2 no docid027973 rev 4 28/115 stm32l011x3/4 functional overview 32 3.14.1 general-purpose ti mers (tim2, tim21) there are three synchronizable general-purpose timers embedded in the stm32l011x3/4 devices (see table 7 for differences). tim2 tim2 is based on 16-bit auto-reload up/down counter. it includes a 16-bit prescaler. it features four independent channels each for input capture/output compare, pwm or one- pulse mode output. the tim2 general-purpose timers can work together or with the tim21 general-purpose timer via the timer link feature for synchroniz ation or event chaining. its counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. tim2 has independent dma request generation. this timer is capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. tim21 tim21 is based on a 16-bit auto-reload up/down c ounter. it includes a 16-bit prescaler. it has two independent channels for input capture/output compare, pwm or one-pulse mode output. it can work together and be synchronized with tim2 full-featured general-purpose timer. it can also be used as simple timebase and be clocked by the lse clock source (32.768 khz) to provide independent timebase from the main cpu clock. 3.14.2 low-power timer (lptim) the low-power timer has an independent clock and is running also in stop mode if it is clocked by lse, lsi or an external clock. it is able to wakeup the devices from stop mode. this low-power timer supports the following features: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous / one shot mode ? selectable software / hardware input trigger ? selectable clock source ? internal clock source: l se, lsi, hsi or apb clock ? external clock source over lptim1 inpu t (working even with no internal clock source running, used by the pulse counter application) ? programmable digital glitch filter ? encoder mode 3.14.3 systick timer this timer is dedicated to the os, but could also be used as a standard downcounter. it is based on a 24-bit downcounter with autore load capability and a programmable clock source. it features a maskable system interr upt generation when the counter reaches ?0?. functional overview stm32l011x3/4 29/115 docid027973 rev 4 3.14.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 37 khz internal rc and, as it operates independently of the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode. 3.14.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.15 communication interfaces 3.15.1 i 2 c bus one i 2 c interface (i2c1) can operate in multimaster or slave modes. the i 2 c interface can support standard mode (sm, up to 100 kbit/s), fast mode (fm, up to 400 kbit/s) and fast mode plus (fm+, up to 1 mbit/s) with 20 ma output drive on some i/os. the i 2 c interface supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, i2c1 provides hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) gener ation/verification, timeouts verifications and alert protocol management. i2c1 also has a clock domain independent from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. the i2c interface can be served by the dma controller. refer to table 9 for the supported modes and features of i2c interface. table 8. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. docid027973 rev 4 30/115 stm32l011x3/4 functional overview 32 3.15.2 universal synchronous/asynchr onous receiver tran smitter (usart) the usart interface (usart2) is able to co mmunicate at speeds of up to 4 mbit/s. it provides hardware management of the cts, rts and rs485 driver enable (de) signals, multiprocessor communication mode and single-wire half-duplex communication mode. usart2 also supports smartcard communication (iso 7816, t=0 protocol) and irda sir endec. usart2 interface can be served by the dma controller. table 10 for the supported modes and features of usart interface. table 9. stm32l011x3/4 i 2 c implementation i2c features (1) 1. x = supported. i2c1 7-bit addressing mode x 10-bit addressing mode x standard mode (up to 100 kbit/s) x fast mode (up to 400 kbit/s) x fast mode plus with 20 ma output drive i/os (up to 1 mbit/s) x (2) 2. see table 13: pin definitions on page 37 for the list of i/os that feature fast mode plus capability independent clock x smbus x wakeup from stop x table 10. usart implementation usart modes/features (1) 1. x = supported. usart2 hardware flow control for modem x continuous communication using dma x multiprocessor communication x synchronous mode - smartcard mode x single-wire half-duplex communication x irda sir endec block x lin mode - dual clock domain and wakeup from stop mode - receiver timeout interrupt - modbus communication - auto baud rate detection (4 modes) - driver enable x functional overview stm32l011x3/4 31/115 docid027973 rev 4 3.15.3 low-power universal asynchron ous receiver transmitter (lpuart) the devices embed one low-power uart. the lpuart supports asynchronous serial communication with minimum power consumption. it supports half duplex single wire communication and modem operations (c ts/rts). it allows multiprocessor communication. the lpuart has a clock domain independent from the cpu clock, and can wake up the system from stop mode, using baudrates up to 46 kbaud. the wakeup events from stop mode are programmable and can be: ? start bit detection ? or any received data frame ? or a specific programmed data frame only a 32.768 khz clock (lse) is needed to allow lpuart communication up to 9600 baud. therefore, even in stop mode, the lpuart can wait for an incoming frame while having an extremely low energy consumption. higher speed clock can be used to reach higher baudrates. lpuart interface can be served by the dma controller. 3.15.4 serial peripheral interface (spi) the spi is able to communicate at up to 16 mbit s/s in slave and master modes in full-duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification support s basic sd card/mmc modes. the spi can be served by the dma controller. refer to table 11 for the supported modes and features of spi interface. 3.16 cyclic redundancy che ck (crc) calculation unit the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compar ed with a reference signature generated at linktime and stored at a given memory location. table 11. spi implementation spi features (1) 1. x = supported. spi1 hardware crc calculation x i2s mode - ti mode x docid027973 rev 4 32/115 stm32l011x3/4 functional overview 32 3.17 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. pin descriptions stm32l011x3/4 33/115 docid027973 rev 4 4 pin descriptions figure 3. stm32l011x3/4 lqfp32 pinout 1. the above figure shows the package top view. figure 4. stm32l011x3/4 ufqfpn32 pinout 1. the above figure shows the package top view. 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 3 & 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 3 $ 3 $ 9 6 6 3 % 3 % 3 % 3 % 3 % 3 $ 3 & 2 6 & b , 1 9 ' ' / 4 ) 3 3 $ & . b , 1 3 % % 2 2 7 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 2 6 & b 2 8 7 9 ' ' $ 3 $ & . b , 1 3 $ 3 $ 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 9 ' ' 3 & 2 6 & b , 1 9 ' ' 9 6 6 1 5 6 7 docid027973 rev 4 34/115 stm32l011x3/4 pin descriptions 42 figure 5. stm32l011x3/4 wlcsp25 pinout 1. the above figure shows the package top view. figure 6. stm32l011x3/4 ufqfpn28 pinout 1. the above figure shows the package top view. 3 $ 3 $ 0 6 y 9 $ % & ' ( 3 $ 9 ' ' 9 6 6 3 $ 3 % 3 $ 3 % 3 % 3 % 3 % 3 % % 2 2 7 3 $ 3 $ 3 & 2 6 & b , 1 3 $ 9 ' ' $ 3 & 2 6 & b 2 8 7 3 $ 3 $ 1 5 6 7 3 $ 3 $ 3 $ & . b , 1 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 % % 2 2 7 3 & 2 6 & b , 1 1 5 6 7 9 ' ' $ 3 $ & . b , 1 3 $ 3 % 3 % 3 % 3 % 3 $ 3 $ 3 % 3 & 2 6 & b 2 8 7 pin descriptions stm32l011x3/4 35/115 docid027973 rev 4 figure 7. stm32l011x3/4 ufqfpn20 pinout 1. the above figure shows the package top view. figure 8. stm32l011x3/4 tssop20 pinout 1. the above figure shows the package top view. 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 & 2 6 & b , 1 1 5 6 7 9 ' ' $ 3 $ & . b , 1 3 % % 2 2 7 3 % 3 % 3 $ 3 $ 3 & 2 6 & b 2 8 7 0 6 y 9 3 % % 2 2 7 1 5 6 7 3 $ 3 $ & . b , 1 3 $ 3 $ 3 $ 3 $ 3 % 9 6 6 3 $ 3 $ 9 ' ' $ 3 $ 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 9 ' ' 3 $ 3 $ 3 $ docid027973 rev 4 36/115 stm32l011x3/4 pin descriptions 42 figure 9. stm32l011x3/4 tssop14 pinout 1. the above figure shows the package top view. 0 6 y 9 3 % % 2 2 7 1 5 6 7 3 $ & . b , 1 3 $ 3 $ 3 $ 9 6 6 3 $ 3 $ 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 9 ' ' 3 $ 3 $ table 12. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets be low the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to the adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers pin descriptions stm32l011x3/4 37/115 docid027973 rev 4 table 13. pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions tssop14 ufqfpn20 tssop20 ufqfpn28 lqfp32 ufqfpn32 (1) wlcsp25 alternate functions additional functions 212222b5 pc14- osc32_in i/o ft - - osc32_in 323333c5 pc15- osc32_out i/o tc - - osc32_out 434444d5 nrst i/orst (2) -- 1045555c4 vdda s - (3)(4) -- 556666e5pa0-ck_ini/otta - usart2_rx, lptim1_in1, tim2_ch1, usart2_cts, tim2_etr, lpuart1_rx, comp1_out comp1_inm, adc_in0, rtc_tamp2/wku p1/ck_in 667777b4 pa1 i/oft - eventout, lptim1_in2, tim2_ch2, i2c1_smba, usart2_rts, tim21_etr, lpuart1_tx comp1_inp, adc_in1 - - 8888d4 pa2 i/otta - tim21_ch1, tim2_ch3, usart2_tx, lpuart1_tx, comp2_out comp2_inm, adc_in2, rtc_tamp3/rtc_ ts/rtc_out/wku p3 - - 9999e4 pa3 i/oft - tim21_ch2, tim2_ch4, usart2_rx, lpuart1_rx comp2_inp, adc_in3 7 7 10 10 10 10 b3 pa4 i/o tta - spi1_nss, lptim1_in1, lptim1_etr, i2c1_scl, usart2_ck, tim2_etr, lpuart1_tx, comp2_out comp1_inm, comp2_inm, adc_in4 docid027973 rev 4 38/115 stm32l011x3/4 pin descriptions 42 - 8 11 11 11 11 d3 pa5 i/o tta - spi1_sck, lptim1_in2, tim2_etr, tim2_ch1 comp1_inm, comp2_inm, adc_in5 - 9 12 12 12 12 e3 pa6 i/o ft - spi1_miso, lptim1_etr, lpuart1_cts, eventout, comp1_out adc_in6 8 1013131313c3 pa7 i/o ft - spi1_mosi, lptim1_out, usart2_cts, tim21_etr, eventout, comp2_out comp2_inp, adc_in7 - - - 14 14 14 e2 pb0 i/o ft - eventout, spi1_miso, tim2_ch2, usart2_rts, tim2_ch3 adc_in8, vref_out - 1114151515d2 pb1 i/o ft - usart2_ck, spi1_mosi, lptim1_in1, lpuart1_rts, tim2_ch4 adc_in9, vref_out -----16- pb2 i/oft - lptim1_out - 9 12 15 16 16 - e1 vss s - (5) -- 10 13 16 17 17 17 d1 vdd s - (6) -- - - - 18 18 18 c1 pa8 i/o ft - mco, lptim1_in1, eventout, usart2_ck, tim2_ch1 - 11 14 17 19 19 19 b1 pa9 i/o ftf - mco, i2c1_scl, lptim1_out, usart2_tx, tim21_ch2, comp1_out - table 13. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions tssop14 ufqfpn20 tssop20 ufqfpn28 lqfp32 ufqfpn32 (1) wlcsp25 alternate functions additional functions pin descriptions stm32l011x3/4 39/115 docid027973 rev 4 12 15 18 20 20 20 c2 pa10 i/o ftf - tim21_ch1, i2c1_sda, rtc_refin, usart2_rx, tim2_ch3, comp1_out - ----2121- pa11 i/oft - spi1_miso, lptim1_out, eventout, usart2_cts, tim21_ch2, comp1_out - ----2222- pa12 i/oft - spi1_mosi, eventout, usart2_rts, comp2_out - 13 16 19 21 23 23 a1 pa13 i/o ftf - swdio, lptim1_etr, i2c1_sda, spi1_sck, lpuart1_rx, comp1_out - 14 17 20 22 24 24 a2 pa14 i/o ft - swclk, lptim1_out, i2c1_smba, usart2_tx, spi1_miso, lpuart1_tx, comp2_out - - - - 23 25 25 - pa15 i/o ft - spi1_nss, tim2_etr, eventout, usart2_rx, tim2_ch1 - - - - 24 26 26 b2 pb3 i/o ft - spi1_sck, tim2_ch2, eventout comp2_inm - - - 25 27 27 - pb4 i/o ft - spi1_miso, eventout comp2_inp table 13. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions tssop14 ufqfpn20 tssop20 ufqfpn28 lqfp32 ufqfpn32 (1) wlcsp25 alternate functions additional functions docid027973 rev 4 40/115 stm32l011x3/4 pin descriptions 42 - - - 26 28 28 - pb5 i/o ft - spi1_mosi, lptim1_in1, i2c1_smba, tim21_ch1 comp2_inp - 18 - 27 29 29 a3 pb6 i/o ftf - usart2_tx, i2c1_scl, lptim1_etr, tim2_ch3, lpuart1_tx comp2_inp - 19 - 28 30 30 a4 pb7 i/o ftf - usart2_rx, i2c1_sda, lptim1_in2, tim2_ch4, lpuart1_rx comp2_inp, vref_pvd_in 1201 13131a5pb9-boot0 i b - - boot0 (boot memory selection) -----32- pb8 i/oftf - usart2_tx, eventout, i2c1_scl, spi1_nss - ----32-- vss s - (5) -- ----11- vdd s - (6) -- 1. v ss pins are connected to the exposed pad (see figure 36: ufqfpn32, 5 x 5 mm, 32-pin package outline ). 2. device reset input/internal reset output (active low). 3. analog power supply. 4. on tssop14 package, v dda is internally connected to v dd . 5. digital and analog ground. 6. digital power supply. table 13. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions tssop14 ufqfpn20 tssop20 ufqfpn28 lqfp32 ufqfpn32 (1) wlcsp25 alternate functions additional functions stm32l011x3/4 pin descriptions docid027973 rev 4 41/115 table 14. alternate functions ports af0 af1 af2 af3 af4 af5 af6 af7 spi1/usart2/ tim21/ eventout/ sys_af spi1/i2c1/ lptim lpuart1/ lptim/tim2/ eventout/ sys_af i2c1/lptim/ eventout i2c1/usart2/l puart1/ eventout spi1/tim2/21 lpuart1/eve ventout comp1/2 port a pa0 usart2_rx lptim1_in1 tim2_ch1 - usart 2_cts tim2_etr lpuart1_rx comp1_out pa1 eventout lptim1_in2 tim2_ch2 i2c1_s mba usart2_rts tim21_etr lpuart1_tx - pa2 tim21_ch1 - tim2_ch3 - usart2_tx - lpuart1_tx comp2_out pa3 tim21_ch2 - tim2_ch4 - usart2_rx - lpuart1_rx - pa4 spi1_nss lptim1_in1 lptim1_etr i2c1_sc l usart2_ck tim2_etr lpuart1_tx comp2_out pa5 spi1_sck lptim1_in2 tim2_etr - - tim2_ch1 - - pa6 spi1_miso lptim1_etr - - lpuart1_cts - eventout comp1_out pa7 spi1_mosi lptim1_out - - usart 2_cts tim21_etr eventout comp2_out pa8 mco - lptim1_in1 eventout usart2_ck tim2_ch1 - - pa9 mco i2c1_scl lptim1_out - usart2_tx tim21_ch2 - comp1_out pa10 tim21_ch1 i2c1_sda rtc_refin - usart2_rx tim2_ch3 - comp1_out pa11 spi1_miso lptim1_out eventout - usart2_cts tim21_ch2 - comp1_out pa12 spi1_mosi - eventout - usart2_rts - - comp2_out pa13 swdio lptim1_etr - i2c1_sda - spi1_sck lpuart1_rx comp1_out pa14 swclk lptim1_out - i2c1_smba usa rt2_tx spi1_miso lpuart1_tx comp2_out pa15 spi1_nss - tim2_etr eventout usart2_rx tim2_ch1 - - pin descriptions stm32l011x3/4 42/115 docid027973 rev 4 port b pb0 eventout spi1_miso tim2_ch2 - usart2_rts tim2_ch3 - - pb1 usart2_ck spi1_mosi lptim1_in1 - lpuart1_rts tim2_ch4 - - pb2 - - lptim1_out - - - - - pb3 spi1_sck - tim2_ch2 - eventout - - - pb4 spi1_miso - eventout - - - - - pb5 spi1_mosi - lptim1_in1 i2c1_smba - tim21_ch1 - - pb6 usart2_tx i2c1_scl lptim1_etr - - tim2_ch3 lpuart1_tx - pb7 usart2_rx i2c1_sda lptim1_in2 - - tim2_ch4 lpuart1_rx - pb8 usart2_tx - eventout - i2c1_scl spi1_nss - - pb9-- - - - --- port c pc14-- - - - --- pc15-- - - - --- table 14. alternate functions (continued) ports af0 af1 af2 af3 af4 af5 af6 af7 spi1/usart2/ tim21/ eventout/ sys_af spi1/i2c1/ lptim lpuart1/ lptim/tim2/ eventout/ sys_af i2c1/lptim/ eventout i2c1/usart2/l puart1/ eventout spi1/tim2/21 lpuart1/eve ventout comp1/2 memory mapping stm32l011x3/4 43/115 docid027973 rev 4 5 memory mapping figure 10. memory map 1. refer to the stm32l011x3/4 reference manual for details on the flash memory organization for each memory size. 0 6 9 5 h v h u y h g , 2 3 2 5 7 [ ) ) ) ) ) ) ) ) 3 h u l s k h u d o v 6 5 $ 0 ) o d v k v \ v w h p p h p r u \ u h v h u y h g 6 \ v w h p p h p r u \ 2 s w l r q e \ w h v [ ( ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h p h q g l q j r q % 2 2 7 f r q i l j x u d w l r q [ [ ( [ & [ $ [ [ [ [ [ [ [ ) ) ) ) ) ) ) u h v h u y h g & 2 ' ( $ 3 % $ 3 % u h v h u y h g [ [ [ [ u h v h u y h g [ $ + % [ u h v h u y h g [ ) ) ) [ ) ) & r u w h [ 0 s h u l s k h u d o v docid027973 rev 4 44/115 stm32l011x3/4 electrical characteristics 92 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.6 v (for the 1.65 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 11 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 12 . figure 11. pin loading conditions figure 12. pin input voltage d l f & s ) 0 & 8 s l q d l f 0 & 8 s l q 9 , 1 electrical characteristics stm32l011x3/4 45/115 docid027973 rev 4 6.1.6 power supply scheme figure 13. power supply scheme 1. on tssop14 package, v dda is internally connected to v dd . 2. v ssa is internally connected to v ss on all packages. 6.1.7 current consumption measurement figure 14. current consum ption measurement scheme 0 6 y 9 $ q d o r j 5 & 3 / / & 2 0 3 ? 9 ' ' * 3 , 2 v 2 8 7 , 1 . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v 6 w d q g e \ s r z h u f l u f x l w u \ 2 6 & 5 7 & : d n h x s o r j l f 5 7 & e d f n x s u h j l v w h u v 1 ? q ) ? ? ) 5 h j x o d w r u 9 6 6 9 ' ' $ 9 6 6 $ $ ' & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) 9 ' ' $ 0 6 y 9 1 [ 9 ' ' , ' ' 1 ? q ) ? ? ) 1 [ 9 6 6 9 ' ' $ docid027973 rev 4 46/115 stm32l011x3/4 electrical characteristics 92 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 15: voltage characteristics , table 16: current characteristics , and table 17: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 15. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 16 for maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v dd +4.0 input voltage on tc pins v ss ? 0.3 4.0 input voltage on boot0 v ss v dd + 4.0 input voltage on any other pin v ss ? 0.3 4.0 | v dd | variations between different v ddx power pins - 50 mv |v dda -v ddx | variations between any v ddx and v dda power pins (3) 3. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and device operation. its value does not need to respect this rule. - 300 | v ss | variations between all different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.11 electrical characteristics stm32l011x3/4 47/115 docid027973 rev 4 table 16. current characteristics symbol ratings max. unit i vdd (2) total current into sum of all v dd power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 105 ma i vss (2) 2. this current consumption must be correctly distri buted over all i/os and control pins. the total output current must not be sunk/sourced between two consecut ive power supply pins referring to high pin count lqfp packages. total current out of sum of all v ss ground lines (sink) (1) 105 i vdd(pin) maximum current into each v dd power pin (source) (1) 100 i vss(pin) maximum current out of each v ss ground pin (sink) (1) 100 i io output current sunk by any i/o and control pin except ftf pins 16 output current sunk by ftf pins 22 output current sourced by any i/o and control pin -16 i io(pin) (3) 3. these values apply only to stm32l01 1gxux part number (ufqfpn28 package). total output current sunk by sum of all ios and control pins (4) 4. this current consumption must be correctly distributed ov er all i/os and control pins. in particular, it must be located the closest possible to the couple of supply and ground, and distributed on both sides. 45 total output current sourced by sum of all ios and control pins -45 i io(pin) total output current sunk by sum of all ios and control pins (2) 90 total output current sourced by sum of all ios and control pins (2) -90 i inj(pin) injected current on ft, fff, rst and b pins -5/+0 (5) 5. positive current injection is not possible on these i/os. a negative injection is induced by v in docid027973 rev 4 48/115 stm32l011x3/4 electrical characteristics 92 6.3 operating conditions 6.3.1 general operating conditions table 18. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 32 mhz f pclk1 internal apb1 clock frequency - 0 32 f pclk2 internal apb2 clock frequency - 0 32 v dd standard operating voltage bor detector disabled 1.65 3.6 v bor detector enabled, at power on 1.8 3.6 bor detector disabled, after power on 1.65 3.6 v dda analog operating voltage (all features) must be the same voltage as v dd (1) 1.65 3.6 v v in input voltage on ft, ftf and rst pins (2) 2.0 v v dd 3.6 v -0.3 5.5 v 1.65 v v dd 2.0 v -0.3 5.2 input voltage on boot0 pin - 0 5.5 input voltage on tc pin - -0.3 v dd +0.3 p d power dissipation at t a = 85 c (range 6) or t a =105 c (rage 7) (3) lqfp32 package - 333 mw ufqfpn32 package - 513 ufqfpn28 package - 206 wlcsp25 package - 286 tssop20 package - 270 ufqfpn20 package - 196 tssop14 package - 210 power dissipation at t a = 125 c (range 3) (3) lqfp32 package - 83 ufqfpn32 package - 128 ufqfpn28 package - 52 wlcsp25 package - 71 tssop20 package - 67 ufqfpn20 package - 49 tssop14 package - 53 electrical characteristics stm32l011x3/4 49/115 docid027973 rev 4 6.3.2 embedded reset and power control block characteristics the parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in table 18 . t a temperature range maximum power dissipation (range 6) ?40 85 c maximum power dissipation (range 7) ?40 105 maximum power dissipation (range 3) ?40 125 t j junction temperature range (range 6) -40 c t a 85 ?40 105 junction temperature range (range 7) -40 c t a 105 c ?40 125 junction temperature range (range 3) -40 c t a 125 c ?40 130 1. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and normal operation. 2. to sustain a voltage higher than v dd +0.3v, the internal pull-up/pull-down resistors must be disabled. 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 17: thermal characteristics on page 47 ). table 18. general operating conditions (continued) symbol parameter conditions min max unit table 19. embedded reset and power control block characteristics symbol parameter conditions min typ max unit t vdd (1) v dd rise time rate bor detector enabled 0 - s/v bor detector disabled 0 - 1000 v dd fall time rate bor detector enabled 20 - bor detector disabled 0 - 1000 t rsttempo (1) reset temporization v dd rising, bor enabled - 2 3.3 ms v dd rising, bor disabled (2) 0.4 0.7 1.6 v por/pdr power on/power down reset threshold falling edge 1 1.5 1.65 v rising edge 1.3 1.5 1.65 v bor0 brown-out reset threshold 0 falling edge 1.67 1.7 1.74 rising edge 1.69 1.76 1.8 v bor1 brown-out reset threshold 1 falling edge 1.87 1.93 1.97 rising edge 1.96 2.03 2.07 v bor2 brown-out reset threshold 2 falling edge 2.22 2.30 2.35 rising edge 2.31 2.41 2.44 docid027973 rev 4 50/115 stm32l011x3/4 electrical characteristics 92 v bor3 brown-out reset threshold 3 falling edge 2.45 2.55 2.6 v rising edge 2.54 2.66 2.7 v bor4 brown-out reset threshold 4 falling edge 2.68 2.8 2.85 rising edge 2.78 2.9 2.95 v pvd0 programmable voltage detector threshold 0 falling edge 1.8 1.85 1.88 rising edge 1.88 1.94 1.99 v pvd1 pvd threshold 1 falling edge 1.98 2.04 2.09 rising edge 2.08 2.14 2.18 v pvd2 pvd threshold 2 falling edge 2.20 2.24 2.28 rising edge 2.28 2.34 2.38 v pvd3 pvd threshold 3 falling edge 2.39 2.44 2.48 rising edge 2.47 2.54 2.58 v pvd4 pvd threshold 4 falling edge 2.57 2.64 2.69 rising edge 2.68 2.74 2.79 v pvd5 pvd threshold 5 falling edge 2.77 2.83 2.88 rising edge 2.87 2.94 2.99 v pvd6 pvd threshold 6 falling edge 2.97 3.05 3.09 rising edge 3.08 3.15 3.20 v hyst hysteresis voltage bor0 threshold - 40 - mv all bor and pvd thresholds excepting bor0 -100- 1. guaranteed by characterization results, not tested in production. 2. valid for device version without bor at power up. please see option "d" in orderi ng information scheme for more details. table 19. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics stm32l011x3/4 51/115 docid027973 rev 4 6.3.3 embedded internal reference voltage the parameters given in table 21 are based on characterization results, unless otherwise specified. table 20. embedded internal reference voltage calibration values calibration value name description memory address vrefint_cal raw data acquired at temperature of 25c v dda = 3 v 0x1ff8 0078 - 0x1ff8 0079 table 21. embedded internal reference voltage (1) symbol parameter conditions min typ max unit v refint out (2) internal reference voltage ? 40 c < t j < +125 c 1.202 1.224 1.242 v t vrefint internal reference startup time - - 2 3 ms v vref_meas v dda voltage during v refint factory measure -2.9933.01v a vref_meas accuracy of factory-measured v refint value (3) including uncertainties due to adc and v dda values -- 5mv t coeff (4) temperature coefficient ?40 c < t j < +125 c - 25 100 ppm/c 0 c < t j < +50 c - - 20 a coeff (4) long-term stability 1000 hours, t= 25 c - - 1000 ppm v ddcoeff (4) voltage coefficient 3.0 v < v dda < 3.6 v - - 2000 ppm/v t s_vrefint (4)(5) adc sampling time when reading the internal reference voltage -510-s t adc_buf (4) startup time of reference voltage buffer for adc ---10s i buf_adc (4) consumption of reference voltage buffer for adc - - 13.5 25 a i vref_out (4) vref_out output current (6) ---1a c vref_out (4) vref_out output load - - - 50 pf i lpbuf (4) consumption of reference voltage buffer for vref_out and comp - - 730 1200 na v refint_div1 (4) 1/4 reference voltage - 24 25 26 % v refint v refint_div2 (4) 1/2 reference voltage - 49 50 51 v refint_div3 (4) 3/4 reference voltage - 74 75 76 1. refer to table 33: peripheral current c onsumption in stop and standby mode for the value of the internal reference current consumption (i refint ). 2. guaranteed by test in production. 3. the internal v ref value is individually measured in produc tion and stored in dedicated eeprom bytes. docid027973 rev 4 52/115 stm32l011x3/4 electrical characteristics 92 6.3.4 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, temperature, i/o pin loadi ng, device software conf iguration, operating frequencies, i/o pin switching rate, program lo cation in memory and executed binary code. the current consumption is measured as described in figure 14: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equival ent to dhrystone 2.1 code if not specified otherwise. the current consumption values are derived from the tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18: general operating conditions unless otherwis e specified. the mcu is placed under the following conditions: ? all i/o pins are configured in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time and pr efetch is adjusted depending on f hclk frequency and voltage range to provide the best cpu performance unless otherwise specified. ? when the peripherals are enabled f apb1 = f apb2 = f apb ? when pll is on, the pll inputs are equal to hsi = 16 mhz (if internal clock is used) or hse = 16 mhz (if hse bypass mode is used) ? the hse user clock is applied to ck_in. it follows the characteristic specified in table 35: high-speed external user clock characteristics ? for maximum current consumption v dd = v dda = 3.6 v is applied to all supply pins ? for typical current consumption v dd = v dda = 3.0 v is applied to all supply pins if not specified otherwise 4. guaranteed by design, not tested in production. 5. shortest sampling time can be determined in the application by multiple iterations. 6. to guarantee less than 1% vref_out deviation. electrical characteristics stm32l011x3/4 53/115 docid027973 rev 4 table 22. current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ max (1) unit i dd (run from flash) supply current in run mode, code executed from flash f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0]=11 1 mhz 140 180 a 2 mhz 245 290 4mhz 460 540 range 2, v core =1.5 v, vos[1:0]=10, 4 mhz 0.56 0.65 ma 8 mhz 1.1 1.3 16 mhz 2.1 2.4 range 1, v core =1.8 v, vos[1:0]=01 8 mhz 1.3 1.6 16 mhz 2.6 3 32 mhz 5.3 6.5 msi clock range 3, v core =1.2 v, vos[1:0]=11 65 khz 34.5 54 a 524 khz 86 120 4.2 mhz 505 560 hsi clock range 2, v core =1.5 v, vos[1:0]=10, 16 mhz 2.2 2.6 ma range 1, v core =1.8 v, vos[1:0]=01 32 mhz 5.4 5.9 1. guaranteed by characterization re sults at 125 c, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). table 23. current consumption in run mode vs code type, code with data processing running from flash symbol parameter conditions f hclk typ unit i dd (run from flash) supply current in run mode, code executed from flash f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (1) range 3, v core =1.2 v, vos[1:0]=11 dhrystone 4 mhz 460 a coremark 440 fibonacci 330 while(1) 305 while(1), prefetch off 320 range 1, vos[1:0]=01, v core =1.8 v dhrystone 32 mhz 5.4 ma coremark 4.9 fibonacci 5 while(1) 4.35 while(1), prefetch off 3.7 1. oscillator bypassed (hsebyp = 1 in rcc_cr register). docid027973 rev 4 54/115 stm32l011x3/4 electrical characteristics 92 figure 15. i dd vs v dd , at t a = 25 c, run mode, code running from flash memory, range 2, 16 mhz hse, 1ws figure 16. i dd vs v dd , at t a = 25 c, run mode, code running from flash memory, range 2, hsi16, 1ws 0 6 y 9 x? x? ? ?x? x x? ? ?x? ?xe ?x ?x? ? ?x? ?xe ?x / ~u s ~ s z????}v ?xu t ^u d a ?? 0 6 y 9 x? x? ? ?x? x x? ? ?x? ?xe ?x ?x? ? ?x? ?xe ?x / ~u s ~ s z????}v ?xu t ^u d a ?? electrical characteristics stm32l011x3/4 55/115 docid027973 rev 4 table 24. current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk typ max (1) unit i dd (run from ram) supply current in run mode, code executed from ram, flash switched off f hse = f hclk up to 16 mhz, included f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 1 mhz 115 140 a 2 mhz 205 240 4 mhz 385 420 range 2, v core =1.5 ,v, vos[1:0]=10 4 mhz 0.48 0.55 ma 8 mhz 0.935 1.1 16 mhz 1.8 2 range 1, v core =1.8 v, vos[1:0]=01 8 mhz 1.1 1.4 16 mhz 2.1 2.5 32 mhz 4.5 4.9 msi clock range 3, v core =1.2 v, vos[1:0]=11 65 khz 22 38 a 524 khz 67 91 4.2 mhz 415 450 hsi16 clock source (16 mhz) range 2, v core =1.5 v, vos[1:0]=10 16 mhz 1.95 2.2 ma range 1, v core =1.8 v, vos[1:0]=01 32 mhz 4.7 5.2 1. guaranteed by char acterization results at 125 c , not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). table 25. current consumption in run mode vs code type, code with data processing running from ram (1) symbol parameter conditions f hclk typ unit i dd (run from ram) supply current in run mode, code executed from ram, flash switched off f hse = f hclk up to 16 mhz, included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 dhrystone 4 mhz 385 a coremark - (3) fibonacci 350 while(1) 340 range 1, v core =1.8 v, vos[1:0]=01 dhrystone 32 mhz 4.5 ma coremark - (3) fibonacci 4.2 while(1) 3 1. guaranteed by characterization results, not te sted in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). 3. coremark code is unable to run from ram since the ram size is only 2 kbytes. docid027973 rev 4 56/115 stm32l011x3/4 electrical characteristics 92 table 26. current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit i dd (sleep) supply current in sleep mode, flash off f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 1 mhz 36.5 70 a 2 mhz 58 95 4 mhz 100 150 range 2, v core =1.5 v, vos[1:0]=10 4 mhz 125 170 8 mhz 230 300 16 mhz 450 540 range 1, v core =1.8 v, vos[1:0]=01 8 mhz 275 350 16 mhz 555 650 32 mhz 1350 1600 msi clock range 3, v core =1.2 v, vos[1:0]=11 65 khz 15.5 32 524 khz 26.5 55 4.2 mhz 115 160 hsi16 clock source (16 mhz) range 2, v core =1.5 v, vos[1:0]=10 16 mhz 585 670 range 1, v core =1.8 v, vos[1:0]=01 32 mhz 1500 1700 supply current in sleep mode, flash on f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 1 mhz 49 88 2 mhz 69 120 4 mhz 115 190 range 2, core =1.5 v, vos[1:0]=10 4 mhz 135 200 8 mhz 240 340 16 mhz 460 650 range 1, v core =1.8 v, vos[1:0]=01 8 mhz 290 400 16 mhz 565 750 32 mhz 1350 1900 msi clock range 3, v core =1.2 v, vos[1:0]=11 65 khz 26.5 46 524 khz 38.5 70 4.2 mhz 125 190 hsi16 clock source (16 mhz) range 2, v core =1.5 v, vos[1:0]=10 16 mhz 600 760 range 1, v core =1.8 v, vos[1:0]=01 32 mhz 1500 1850 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). electrical characteristics stm32l011x3/4 57/115 docid027973 rev 4 table 27. current consumption in low-power run mode symbol parameter conditions typ max (1) unit i dd (lp run) supply current in low-power run mode all peripherals off, code executed from ram, flash switched off, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 5.7 8.1 a t a = 85 c 6.5 9 t a = 105 c 8 13 t a = 125 c 11.5 22 msi clock, 65 khz f hclk = 65 khz t a =-40 c to 25 c 8.7 11 t a = 85 c 9.5 12 t a = 105 c 11 15 t a = 125 c 15 24 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 17 19 t a = 55 c 17 19.5 t a = 85 c 17.5 20 t a = 105 c 19 22 t a = 125 c 22.5 31 all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 18 22 t a = 85 c 20 24 t a = 105 c 22 27 t a = 125 c 26.5 37 msi clock, 65 khz f hclk = 65 khz t a = -40 c to 25 c 22 25 t a = 85 c 24 27 t a = 105 c 26 30 t a = 125 c 30.5 39 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 32 34 t a = 55 c 32.5 35 t a = 85 c 34 37 t a = 105 c 36 39 t a = 125 c 40 47 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified. docid027973 rev 4 58/115 stm32l011x3/4 electrical characteristics 92 figure 17. i dd vs v dd , at t a = -40/25/55/ 85/105/125 c, low-power run mode, code running from ram, range 3, msi (range 0) at 64 khz, 0 ws 0 6 y 9 table 28. current consumption in low-power sleep mode symbol parameter conditions typ max (1) unit i dd (lp sleep) supply current in low-power sleep mode all peripherals off, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz flash off t a = -40 c to 25 c 2.5 (2) - a msi clock, 65 khz f hclk = 32 khz flash on t a = -40 c to 25 c 13 19 t a = 85 c 15.5 20 t a = 105 c 17.5 22 t a = 125 c 21 29 msi clock, 65 khz f hclk = 65 khz, flash on t a = -40 c to 25 c 13.5 19 t a = 85 c 16 20 t a = 105 c 18 22 t a = 125 c 21.5 29 msi clock, 131 khz f hclk = 131 khz, flash on t a = -40 c to 25 c 15.5 21 t a = 55 c 17 22 t a = 85 c 18 23 t a = 105 c 19.5 24 t a = 125 c 23.5 31 1. guaranteed by characterization results at 125 c, not tested in production, unl ess otherwise specified. 2. as the cpu is in sleep mode, the difference between the cu rrent consumption with flas h memory on and off (nearly 12 a) is the same whatever the clock frequency. electrical characteristics stm32l011x3/4 59/115 docid027973 rev 4 figure 18. i dd vs v dd , at t a = -40/25/55/ 85/105/125 c, stop mode with rtc enabled and running on lse low drive figure 19. i dd vs v dd , at t a = -40/25/55/85/105/125 c, st op mode with rtc disabled, all clocks off table 29. typical and maximum current consumptions in stop mode symbol parameter conditions typ max (1) 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified. unit i dd (stop) supply current in stop mode t a = -40c to 25c 0.34 0.99 a t a = 55c 0.43 1.9 t a = 85c 0.94 4.2 t a = 105c 2.0 9 t a = 125c 4.9 19 0 6 y 9 ? ? e ? x x? ? ?x? ?xe ?x ?x? ? ?x? ?xe ?x s ~ s re ?? ?? ?? ? ?? 0 6 y 9 ? ? e ? x x? ? ?x? ?xe ?x ?x? ? ?x? ?xe ?x s ~ s re ?? ?? ?? ? ?? docid027973 rev 4 60/115 stm32l011x3/4 electrical characteristics 92 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in the following tables. the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on table 30. typical and maximum current consumptions in standby mode symbol parameter conditions typ max (1) unit i dd (standby) supply current in standby mode independent watchdog and lsi enabled t a = -40 c to 25 c 0.8 1.6 a t a = 55 c 0.9 1.8 t a = 85 c 1 2 t a = 105 c 1.25 3 t a = 125 c 2 7 independent watchdog and lsi off t a = -40 c to 25 c 0.23 0.6 t a = 55 c 0.25 0.7 t a = 85 c 0.36 1 t a = 105 c 0.62 1.7 t a = 125 c 1.35 5 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified table 31. average current consumption during wakeup symbol parameter system frequency current consumption during wakeup unit i dd (wu from stop) supply current during wakeup from stop mode hsi 1 ma hsi/4 0,7 msi 4,2 mhz 0,7 msi 1,05 mhz 0,4 msi 65 khz 0,1 i dd (reset) reset pin pulled down - 0,21 i dd (power up) bor on - 0,23 i dd (wu from standby) with fast wakeup set msi 2,1 mhz 0,5 with fast wakeup disabled msi 2,1 mhz 0,12 electrical characteristics stm32l011x3/4 61/115 docid027973 rev 4 table 32. peripheral current consumption in run or sleep mode (1) 1. data based on differential i dd measurement between all peripherals off an one peripheral with clock enabled, in the following conditions: f hclk = 32 mhz (range 1), f hclk = 16 mhz (range 2), f hclk = 4 mhz (range 3), f hclk = 64khz (low-power run/sleep), f apb1 = f hclk , f apb2 = f hclk , default prescaler value for each peripheral. the cpu is in sleep mode in both cases. no i/o pins toggling. not tested in production. peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core =1.8 v vos[1:0] = 01 range 2, v core =1.5 v vos[1:0] = 10 range 3, v core =1.2 v vos[1:0] = 11 low-power sleep and run apb1 wwdg 2.5 2 1.6 2 a/mhz (f hclk ) lpuart1 8.3 7.2 5.4 7.2 i2c1 11 8.2 6.8 8.9 lptim1 14 11 8.7 11 tim2 10.5 8.5 6.4 8.5 usart2 8.5 6.8 5.4 7.1 apb2 adc1 (2) 2. hsi oscillator is off for this measure. 5.0 3.9 3.3 4 a/mhz (f hclk ) spi1 4.5 3.5 2.9 3.6 tim21 6.8 6.1 4.5 5.6 dbgmcu 1.7 1.7 1.1 1.4 syscfg/ comp 2.5 2.4 1.6 2.3 cortex- m0+ core i/o port gpioa 7.6 6.3 4.9 6.5 a/mhz (f hclk ) gpiob 5.1 4.1 3.2 4 gpioc 1.1 0.7 0.6 0.8 ahb crc 1.5 1.1 1 1.2 a/mhz (f hclk ) flash (3) 3. these values correspond to the flash memory dynami c current consumption. the flash memory static consumption (flash memory on) equals 12 a and does not depend on the frequency. the flash memory consumption is already taken into account in all the supply cu rrent consumption tables (flash memory on cases). 10 8.5 7 8.5 dma1 5.3 4.2 3.5 4.8 all enabled 96 80 62 88 pwr 2.1 1.9 1.4 1.8 a/mhz (f hclk ) docid027973 rev 4 62/115 stm32l011x3/4 electrical characteristics 92 6.3.5 wakeup time from low-power mode the wakeup times given in the following table are measured with the msi or hsi16 rc oscillator. the clock source us ed to wake up the device d epends on the cu rrent op erating mode: ? sleep mode: the clock source is the clock that was set before entering sleep mode ? stop mode: the clock source is either the ms i oscillator in the range configured before entering stop mode, the hsi16 or hsi16/4. ? standby mode: the clock source is the msi oscillator running at 2.1 mhz all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18 . table 33. peripheral current consumption in stop and standby mode symbol peripheral typical consumption, t a = 25 c unit v dd =1.8 v v dd =3.0 v i dd(pvd / bor) -0.61 a i refint -1.251.3 - lse low drive 0.11 0.16 - lptim1, input 100 hz 0.01 0.02 - lptim1, input 1 mhz 8 9 - lpuart1 0.025 0.027 -rtc0.10.19 table 34. low-power mode wakeup timings symbol parameter conditions typ max unit t wusleep wakeup from sleep mode f hclk = 32 mhz 7 8 cpu cycles t wusleep_lp wakeup from low-power sleep mode, f hclk = 262 khz f hclk = 262 khz flash enabled 78 f hclk = 262 khz flash switched off 910 electrical characteristics stm32l011x3/4 63/115 docid027973 rev 4 t wustop wakeup from stop mode, regulator in run mode f hclk = f msi = 4.2 mhz 5.1 8 s f hclk = f hsi = 16 mhz 5.1 7 f hclk = f hsi /4 = 4 mhz 8.1 11 wakeup from stop mode, regulator in low-power mode f hclk = f msi = 4.2 mhz voltage range 1 58 f hclk = f msi = 4.2 mhz voltage range 2 58 f hclk = f msi = 4.2 mhz voltage range 3 58 f hclk = f msi = 2.1 mhz 7.4 13 f hclk = f msi = 1.05 mhz 14 23 f hclk = f msi = 524 khz 28 38 f hclk = f msi = 262 khz 51 65 f hclk = f msi = 131 khz 99 120 f hclk = f msi = 65 khz 196 260 f hclk = f hsi = 16 mhz 5.1 7 f hclk = f hsi /4 = 4 mhz 8.2 11 wakeup from stop mode, regulator in low-power mode, hsi kept running in stop mode f hclk = f hsi = 16 mhz 3.25 - wakeup from stop mode, regulator in low-power mode, code running from ram f hclk = f hsi = 16 mhz 4.9 7 f hclk = f hsi /4 = 4 mhz 7.9 10 f hclk = f msi = 4.2 mhz 4.8 8 t wustdby wakeup from standby mode fwu bit = 1 f hclk = f msi = 2.1 mhz 65 130 wakeup from standby mode fwu bit = 0 f hclk = f msi = 2.1 mhz 2.2 3 ms table 34. low-power mode wakeup timings (continued) symbol parameter conditions typ max unit docid027973 rev 4 64/115 stm32l011x3/4 electrical characteristics 92 6.3.6 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the input pin is a standard gpio.the external clock signal has to respect the i/o characteristics in section 6.3.12 . however, the recommended clock input waveform is shown in figure 20 . figure 20. high-speed external clock source ac timing diagram table 35. high-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit f hse_ext user external clock source frequency css is on or pll is used 1832mhz css is off, pll not used 0832mhz v hseh ck_in input pin high level voltage - 0.7v dd -v dd v v hsel ck_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) ck_in high or low time 12 - - ns t r(hse) t f(hse) ck_in rise or fall time - - 20 c in(hse) ck_in input capacitance - 2.6 - pf ducy (hse) duty cycle 45 - 55 % i l ck_in input leakage current v ss v in v dd --1a 0 6 y 9 & . b , 1 ( ; 7 ( 5 1 $ / 6 7 0 / [ [ & / 2 & . 6 2 8 5 & ( 9 + 6 ( + w i + 6 ( w : + 6 ( , / 7 + 6 ( w w u + 6 ( w : + 6 ( i + 6 ( b h [ w 9 + 6 ( / electrical characteristics stm32l011x3/4 65/115 docid027973 rev 4 low-speed external user clock generated from an external source the characteristics given in the following table result from tests performed using a low- speed external clock source, and under ambien t temperature and supply voltage conditions summarized in table 18 . figure 21. low-speed external clock source ac timing diagram low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 37 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization table 36. low-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production symbol parameter conditions min typ max unit f lse_ext user external clock source frequency - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t w(lse) osc32_in high or low time 465 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 10 c in(lse) osc32_in input capacitance - - 0.6 - pf ducy (lse) duty cycle - 45 - 55 % i l osc32_in input leakage current v ss v in v dd --1a d l f 2 6 & b , 1 ( ; 7 ( 5 1 $ / 6 7 0 / [ [ & / 2 & . 6 2 8 5 & ( 9 / 6 ( + w i / 6 ( w : / 6 ( , / 7 / 6 ( w w u / 6 ( w : / 6 ( i / 6 ( b h [ w 9 / 6 ( / docid027973 rev 4 66/115 stm32l011x3/4 electrical characteristics 92 time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website http://www.st.com . figure 22. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. table 37. lse oscillator characteristics (1) symbol parameter conditions (2) min (2) typ max unit f lse lse oscillator frequency - 32.768 - khz g m maximum critical crystal transconductance lsedrv[1:0]=00 lower driving capability --0.5 a/v lsedrv[1:0]= 01 medium low driving capability - - 0.75 lsedrv[1:0] = 10 medium high driving capability --1.7 lsedrv[1:0]=11 higher driving capability --2.7 t su(lse) (3) startup time v dd is stabilized - 2 - s 1. guaranteed by design, not tested in production. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. guaranteed by characterization results, not tested in production. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manuf acturer. to increase speed, address a lower-drive quartz with a high- driver mode. 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i / 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / electrical characteristics stm32l011x3/4 67/115 docid027973 rev 4 6.3.7 internal clock source characteristics the parameters given in table 38 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18 . high-speed internal 16 mhz (hsi16) rc oscillator figure 23. hsi16 minimum and maxi mum value versus temperature table 38. 16 mhz hsi16 oscillator characteristics symbol parameter conditions min typ max unit f hsi16 frequency v dd = 3.0 v - 16 - mhz trim (1)(2) 1. the trimming step differs depending on the trimming code. it is usually negativ e on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xe0). hsi16 user- trimmed resolution trimming code is not a multiple of 16 - 0.4 0.7 % trimming code is a multiple of 16 - - 1.5 % acc hsi16 (2) 2. guaranteed by characterization re sults, not tested in production. accuracy of the factory-calibrated hsi16 oscillator v dda = 3.0 v, t a = 25 c -1 (3) 3. guaranteed by test in production. -1 (3) % v dda = 3.0 v, t a = 0 to 55 c -1.5 - 1.5 % v dda = 3.0 v, t a = -10 to 70 c -2 - 2 % v dda = 3.0 v, t a = -10 to 85 c -2.5 - 2 % v dda = 3.0 v, t a = -10 to 105 c -4 - 2 % v dda = 1.65 v to 3.6 v t a = -40 to 125 c -5.45 - 3.25 % t su(hsi16) (2) hsi16 oscillator startup time - - 3.7 6 s i dd(hsi16) (2) hsi16 oscillator power consumption - - 100 140 a 0 6 y 9 9 p l q 9 w \ s 9 p d [ 9 p d [ 9 p l q docid027973 rev 4 68/115 stm32l011x3/4 electrical characteristics 92 low-speed internal (lsi) rc oscillator multi-speed internal (msi) rc oscillator table 39. lsi oscillator characteristics symbol parameter min typ max unit f lsi (1) 1. guaranteed by test in production. lsi frequency 26 38 56 khz d lsi (2) 2. this is a deviation for an individual part, once the init ial frequency has been measured. lsi oscillator frequency drift 0c t a 85c -10 - 4 % t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - - 200 s i dd(lsi) (3) lsi oscillator power consumption - 400 510 na table 40. msi oscillator characteristics symbol parameter condition typ max unit f msi frequency after factory calibration, done at v dd = 3.3 v and t a = 25 c msi range 0 65.5 - khz msi range 1 131 - msi range 2 262 - msi range 3 524 - msi range 4 1.05 - mhz msi range 5 2.1 - msi range 6 4.2 - acc msi frequency error after factory calibration - 0.5 - % d temp(msi) (1) msi oscillator frequency drift 0c t a 85 c - 3-% d volt(msi) (1) msi oscillator frequency drift 1.65 v v dd 3.6 v, t a = 25 c --2.5%/v i dd(msi) (2) msi oscillator power consumption msi range 0 0.75 - a msi range 1 1 - msi range 2 1.5 - msi range 3 2.5 - msi range 4 4.5 - msi range 5 8 - msi range 6 15 - electrical characteristics stm32l011x3/4 69/115 docid027973 rev 4 6.3.8 pll characteristics the parameters given in table 41 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18 . t su(msi) msi oscillator startup time msi range 0 30 - s msi range 1 20 - msi range 2 15 - msi range 3 10 - msi range 4 6 - msi range 5 5 - msi range 6, voltage range 1 and 2 3.5 - msi range 6, voltage range 3 5- t stab(msi) (2) msi oscillator stabilization time msi range 0 - 40 s msi range 1 - 20 msi range 2 - 10 msi range 3 - 4 msi range 4 - 2.5 msi range 5 - 2 msi range 6, voltage range 1 and 2 -2 msi range 3, voltage range 3 -3 f over(msi) msi oscillator frequency overshoot any range to range 5 -4 mhz any range to range 6 -6 1. this is a deviation for an individual part, once the init ial frequency has been measured. 2. guaranteed by characterization results, not tested in production. table 40. msi oscillator characteristics (continued) symbol parameter condition typ max unit table 41. pll characteristics symbol parameter value unit min typ max (1) f pll_in pll input clock (2) 2- 24mhz pll input clock duty cycle 45 - 55 % docid027973 rev 4 70/115 stm32l011x3/4 electrical characteristics 92 6.3.9 memory characteristics ram memory f pll_out pll output clock 2 - 32 mhz t lock pll input = 16 mhz pll vco = 96 mhz - 115 160 s jitter cycle-to-cycle jitter - 600 ps i dda (pll) current consumption on v dda - 220 450 a i dd (pll) current consumption on v dd - 120 150 1. guaranteed by characterization results, not tested in production. 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . table 41. pll characteristics (continued) symbol parameter value unit min typ max (1) table 42. ram and hardware registers symbol parameter cond itions min typ max unit vrm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in stop mode or under reset) or in hardware registers (only in stop mode). stop mode (or reset) 1.65 - - v electrical characteristics stm32l011x3/4 71/115 docid027973 rev 4 flash memory and data eeprom table 43. flash memo ry and data eeprom characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit v dd operating voltage read / write / erase -1.65-3.6v t prog programming time for word or half-page erasing - 3.28 3.94 ms programming - 3.28 3.94 i dd average current during the whole programming / erase operation t a = 25 c, v dd = 3.6 v - 500 700 a maximum current (peak) during the whole programming / erase operation -1.52.5ma table 44. flash memory and data eeprom endurance and retention symbol parameter conditions value unit min (1) 1. guaranteed by characterization re sults, not tested in production. n cyc (2) cycling (erase / write) program memory t a = -40c to 105 c 10 kcycles cycling (erase / write) eeprom data memory 100 cycling (erase / write) program memory t a = -40c to 125 c 0.2 cycling (erase / write) eeprom data memory 2 t ret (2) 2. characterization is done according to jedec jesd22-a117. data retention (program memory) after 10 kcycles at t a = 85 c t ret = +85 c 30 years data retention (eeprom data memory) after 100 kcycles at t a = 85 c 30 data retention (program memory) after 10 kcycles at t a = 105 c t ret = +105 c 10 data retention (eeprom data memory) after 100 kcycles at t a = 105 c data retention (program memory) after 200 cycles at t a = 125 c t ret = +125 c data retention (eeprom data memory) after 2 kcycles at t a = 125 c docid027973 rev 4 72/115 stm32l011x3/4 electrical characteristics 92 6.3.10 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 45 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. table 45. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp32, t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp32, t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-4 4a electrical characteristics stm32l011x3/4 73/115 docid027973 rev 4 to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.11 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/jedec standard. static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. table 46. emi characteristics symbol parameter conditions monitored frequency band max vs. frequency range (32 mhz voltage range 1) unit s emi peak level v dd = 3.3 v, t a = 25 c, lqfp32 package compliant with iec 61967-2 0.1 to 30 mhz -22 dbv 30 to 130 mhz -7 130 mhz to 1ghz -12 sae emi level 1 - table 47. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization re sults, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to ansi/jedec js-001 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1. c4 500 docid027973 rev 4 74/115 stm32l011x3/4 electrical characteristics 92 6.3.12 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection acci dentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or ot her functional failure (for ex ample reset occurrence oscillator frequency deviation). the test results are given in the table 49 . table 48. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +125 c conforming to jesd78a ii level a table 49. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 -0 na ma injected current on all ft pins -5 (1) 1. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. na injected current on any other pin -5 (1) +5 electrical characteristics stm32l011x3/4 75/115 docid027973 rev 4 6.3.13 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 50 are derived from tests performed under the conditions summarized in table 18 . all i/os are cmos and ttl compliant. table 50. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage tc, ft, ftf, rst i/os - - 0.3v dd v boot0 pin - - 0.14v dd (1) v ih input high level voltage all i/os except boot0 pin 0.7 v dd -- boot0 pin 0.15 v dd +0.56 (1) -- v hys i/o schmitt trigger voltage hysteresis (2) standard i/os - 10% v dd (3) - boot0 pin - 0.01 - i lkg input leakage current (4) v ss v in v dd all i/os except boot0 and ftf i/os --50na boot0 (5) v in = v dd -+2- a boot0 v in = v ss -0- v dd v in 5v ft i/os --200 na v dd v in 5v ftf i/os --500 v dd v in 5v boot0 - - 10 a r pu weak pull-up equivalent resistor (6) v in = v ss 30 45 60 k r pd weak pull-down equivalent resistor (6) v in = v dd 30 45 60 k c io i/o pin capacitance - - 5 - pf 1. g uaranteed by characterization, not tested in production 2. hysteresis voltage between schmitt trigger switching levels. guaranteed by characteri zation results, not tested in production . 3. with a minimum of 200 mv. guaranteed by c haracterization results, not tested in production. 4. the max. value may be exceeded if negative current is injected on adjacent pins. 5. boot0/pb9 pin limitation: typi cal input leakage current = 2 a and input frequency limited to 10 khz (1.65 v < v dd < 2.7 v) and 5 mhz (2.7 v < v dd <3.6v). 6. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order). docid027973 rev 4 76/115 stm32l011x3/4 electrical characteristics 92 figure 24. v ih /v il versus vdd (cmos i/os) figure 25. v ih /v il versus vdd (ttl i/os) output driving current the gpios (general purpose input/outputs) can si nk or source up to 8 ma, and sink or source up to 15 ma with the non-standard v ol /v oh specifications given in table 51 . in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd( ) (see table 16 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss( ) (see table 16 ). output voltage levels unless otherwise specified, the parameters given in table 51 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in 0 6 y 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' d o o s l q v h [ f h s w % 2 2 7 3 & 3 + 9 , + p l q 9 ' ' i r u % 2 2 7 3 & 3 + , q s x w u d q j h q r w j x d u d q w h h g 0 6 y 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 9 , / p d [ 9 ' ' 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 , q s x w u d q j h q r w j x d u d q w h h g 9 , + p l q 9 ' ' d o o s l q v h [ f h s w % 2 2 7 3 & 3 + 9 , + p l q 9 ' ' i r u % 2 2 7 3 & 3 + electrical characteristics stm32l011x3/4 77/115 docid027973 rev 4 table 18 . all i/os are cmos and ttl compliant. table 51. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always respect the absolute maximum rating specified in table 16 . the sum of the currents sunk by all the i/os (i/o ports and control pins) must always be respected and must not exceed i io(pin) . output low level voltage for an i/o pin cmos port (2) , i io = +8 ma 2.7 v v dd 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 16 . the sum of the currents sourced by all the i/o s (i/o ports and control pins) must always be respected and must not exceed i io(pin) . output high level voltage for an i/o pin v dd -0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) , i io =+ 8 ma 2.7 v v dd 3.6 v -0.4 v oh (3)(4) 4. guaranteed by characterization results, not tested in production. output high level voltage for an i/o pin ttl port (2) , i io = -6 ma 2.7 v v dd 3.6 v 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io = +15 ma 2.7 v v dd 3.6 v -1.3 v oh (3)(4) output high level voltage for an i/o pin i io = -15 ma 2.7 v v dd 3.6 v v dd -1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +4 ma 1.65 v v dd < 3.6 v -0.45 v oh (3)(4) output high level voltage for an i/o pin i io = -4 ma 1.65 v v dd 3.6 v v dd -0.45 - v olfm+ (1)(4) output low level voltage for an ftf i/o pin in fm+ mode i io = 20 ma 2.7 v v dd 3.6 v -0.4 i io = 10 ma 1.65 v v dd 3.6 v -0.4 docid027973 rev 4 78/115 stm32l011x3/4 electrical characteristics 92 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 26 and table 52 , respectively. unless otherwise specified, the parameters given in table 52 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18 . table 52. i/o ac characteristics (1)(2) ospeedrx [1:0] bit value (1) symbol parameter conditions min max (3) unit 00 f max(io)out maximum frequency (4) c l = 50 pf, v dd = 2.7 v to 3.6 v - 400 khz c l = 50 pf, v dd = 1.65 v to 2.7 v - 100 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 125 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 320 01 f max(io)out maximum frequency (4) c l = 50 pf, v dd = 2.7 v to 3.6 v - 2 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 0.6 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 65 10 f max(io)out maximum frequency (4) c l = 50 pf, v dd = 2.7 v to 3.6 v - 10 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 2 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 13 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 28 11 f max(io)out maximum frequency (4) c l = 30 pf, v dd = 2.7 v to 3.6 v - 35 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 10 t f(io)out t r(io)out output rise and fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 6 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 17 -t extipw pulse width of external signals detected by the exti controller -8-ns 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the line reference m anual for a description of gpio port configuration register. 2. boot0/pb9 maximum input frequency is 10 khz (1.65 v < v dd < 2.7 v) and 5 mhz (2.7 v < v dd <3.6v). 3. guaranteed by design. not tested in production. 4. the maximum frequency is defined in figure 26 . electrical characteristics stm32l011x3/4 79/115 docid027973 rev 4 figure 26. i/o ac charac teristics definition 6.3.14 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu , except when it is internally driven low (see table 53 ). unless otherwise specified, the parameters given in table 53 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18 . d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w table 53. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) nrst input low level voltage - - - 0.3v dd v v ih(nrst) (1) nrst input high level voltage - 0.39v dd + 0.59 -- v ol(nrst) (1) nrst output low level voltage i ol = 2 ma 2.7 v < v dd < 3.6 v -- 0.4 i ol = 1.5 ma 1.65 v < v dd < 2.7 v -- v hys(nrst) (1) nrst schmitt trigger voltage hysteresis --10%v dd (2) -mv r pu weak pull-up equivalent resistor (3) v in = v ss 30 45 60 k v f(nrst) (1) nrst input filtered pulse - - - 50 ns v nf(nrst) (1) nrst input not filtered pulse - 350 - - ns 1. guaranteed by design, not tested in production. 2. 200 mv minimum value 3. the pull-up is designed with a true resist ance in series with a switchable pmos. this pmos contribution to the series resistance is around 10%. docid027973 rev 4 80/115 stm32l011x3/4 electrical characteristics 92 figure 27. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 53 . otherwise the reset will not be taken into account by the device. 6.3.15 12-bit adc characteristics unless otherwise specified, the parameters given in table 54 are values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions summarized in table 18: general operating conditions . note: it is recommended to perform a calibration after each power-up. d l f 6 7 0 / [ [ 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o u h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w table 54. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on fast channel 1.65 - 3.6 v standard channels 1.75 (1) -3.6 i dda (adc) current consumption of the adc on v dda 1.14 msps - 200 - a 10 ksps - 40 - current consumption of the adc on v dd (2) 1.14 msps - 70 - 10 ksps - 1 - f adc adc clock frequency voltage scaling range 1 0.14 - 16 mhz voltage scaling range 2 0.14 - 8 voltage scaling range 3 0.14 - 4 f s (3) sampling rate - 0.05 - 1.14 mhz f trig (3) external trigger frequency f adc = 16 mhz, 16-bit resolution - - 941 khz ---171/f adc v ain conversion voltage range - 0 - v dda v r ain (3) external input impedance see equation 1 and ta ble 55 for details --50k r adc (3)(4) sampling switch resistance - - - 1 k c adc (3) internal sample and hold capacitor ---8pf electrical characteristics stm32l011x3/4 81/115 docid027973 rev 4 equation 1: r ain max formula the simplified formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). t cal (3) calibration time f adc = 16 mhz 5.2 s -831/f adc w latency adc_dr register write latency adc clock = hsi16 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles - adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (3) trigger conversion latency f adc = f pclk /2 = 16 mhz 0.266 s f adc = f pclk /2 8.5 1/f pclk f adc = f pclk /4 = 8 mhz 0.516 s f adc = f pclk /4 16.5 1/f pclk f adc = f hsi16 = 16 mhz 0.252 - 0.260 s jitter adc adc jitter on trigger conversion f adc = f hsi16 -1-1/f hsi16 t s (3) sampling time f adc = 16 mhz 0.093 - 10.03 s - 1.5 - 239.5 1/f adc t stab (3) power-up time - 0 0 1 s t conv (3) total conversion time (including sampling time) f adc = 16 mhz 0.875 10.81 s - 14 to 173 (t s for sampling +12.5 for successive approximation) 1/f adc 1. v dda minimum value can be decreased in spec ific temperature conditions. refer to table 55: rain max for fadc = 16 mhz . 2. a current consumption proportional to the apb clock frequency has to be added (see table 32: peripheral current consumption in run or sleep mode ). 3. guaranteed by design, not tested in production. 4. standard channels have an extra protection resistan ce which depends on supply voltage. refer to table 55: rain max for fadc = 16 mhz . table 54. adc characteristics (continued) symbol parameter conditions min typ max unit r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? < docid027973 rev 4 82/115 stm32l011x3/4 electrical characteristics 92 table 55. r ain max for f adc = 16 mhz (1) t s (cycles) t s (s) r ain max for fast channels (k ) r ain max for standard channels (k ) v dd > 2.7 v v dd > 2.4 v v dd > 2.0 v v dd > 1.8 v v dd > 1.75 v v dd > 1.65 v and t a > ? 10 c v dd > 1.65 v and t a > 25 c 1.5 0.09 0.5 < 0.1 na na na na na na 3.5 0.22 1 0.2 < 0.1 na na na na na 7.5 0.47 2.5 1.7 1.5 < 0.1 na na na na 12.5 0.78 4 3.2 3 1 na na na na 19.5 1.22 6.5 5.7 5.5 3.5 na na na < 0.1 39.5 2.47 13 12.2 12 10 na na na 5 79.5 4.97 27 26.2 26 24 < 0.1 na na 19 160.5 10.03 50 49.2 49 47 32 < 0.1 < 0.1 42 1. guaranteed by design. table 56. adc accuracy (1)(2)(3)(4) symbol parameter conditions min typ max unit et total unadjusted error 1.65 v < v dda < 3.6 v, range 1/2/3, except for tssop14 package -2 4 lsb eo offset error - 1 2.5 eg gain error - 1 2 el integral linearity error - 1.5 2.5 ed differential linearity error - 1 1.5 enob effective number of bits 10.2 11 bits effective number of bits (16-bit mode oversampling with ratio =256) (5) 11.3 12.1 - sinad signal-to-noise distortion 62 67.8 - db snr signal-to-noise ratio 63 68 - signal-to-noise ratio (16-bit mode oversampling with ratio =256) (5) 70 76 - thd total harmonic distortion - -81 -68.5 electrical characteristics stm32l011x3/4 83/115 docid027973 rev 4 figure 28. adc accuracy characteristics et total unadjusted error 1.65 v < v dda < 3.6 v, range 1/2/3, tssop14 package -3 5 lsb eo offset error - 2 2.5 eg gain error - 2 2.5 el integral linearity error - 1.5 2.5 ed differential linearity error - 1 1.7 enob effective number of bits 9.5 10.5 - bits effective number of bits (16-bit mode oversampling with ratio =256) (5) 10.7 11.6 - sinad signal-to-noise distortion 59 65 - db snr signal-to-noise ratio 59 65 - signal-to-noise ratio (16-bit mode oversampling with ratio =256) (5) 66 73 - thd total harmonic distortion - -75 -63 1. adc dc accuracy values are meas ured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negativ e current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the ac curacy of the conversion bei ng performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.12 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. in tssop14 package, where v dda pin is shared with v dd pin, i/o toggling should be minimiz ed to reach the values given in the above table. i/o toggling with l oaded i/o pins can generate ripple on v dd /v dda and degrade the adc accuracy. 5. this number is obtained by the test boar d without additional noise, resulting in non-optimized value for oversampling mode. table 56. adc accuracy (1)(2)(3)(4) symbol parameter conditions min typ max unit ( 7 7 r w d o 8 q d m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h v ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h 9 ' ' $ 9 6 6 $ ( 2 ( 7 ( / ( * ( ' / 6 % , ' ( $ / 0 6 9 docid027973 rev 4 84/115 stm32l011x3/4 electrical characteristics 92 figure 29. typical connecti on diagram using the adc 1. refer to table 54: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 6.3.16 temperature sensor characteristics 0 6 y 9 9 ' ' $ $ , 1 [ , / ? q $ 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 7 5 $ ' & e l w f r q y h u w h u & $ ' & 6 d p s o h d q g k r o g $ ' & f r q y h u w h u table 57. temperature sensor calibration values calibration value name description memory address ts_cal2 ts adc raw data acquired at temperature of 130 c 5c, v dda = 3 v 10 mv 0x1ff8 007e - 0x1ff8 007f table 58. temperature sensor characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by characterization results, not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope 1.48 1.61 1.75 mv/c v 130 voltage at 130c 5c (2) 2. measured at v dd = 3 v 10 mv. v30 adc conversion result is stored in the ts_cal1 byte. 640 670 700 mv i dda (temp) (3) current consumption - 3.4 6 a t start (3) 3. guaranteed by design, not tested in production. startup time - - 10 s t s_temp (4)(3) 4. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 10 - - electrical characteristics stm32l011x3/4 85/115 docid027973 rev 4 6.3.17 comparators table 59. comparator 1 characteristics symbol parameter conditions min (1) typ max (1) 1. guaranteed by characterization, not tested in production. unit v dda analog supply voltage - 1.65 3.6 v r 400k r 400k value - - 400 - k r 10k r 10k value - - 10 - v in comparator 1 input voltage range -0.6-v dda v t start comparator startup time - - 7 10 s td propagation delay (2) 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. --310 v offset comparator offset (3) 3. in tssop14 package, where v dda pin is shared with v dd pin, i/o toggling should be minimized to reach the values given in the above table. i/o toggl ing with loaded i/o pins can generate ripple on v dd /v dda and degrade the comparator performance. -- 3 10 mv d voffset /dt comparator offset variation in worst voltage stress conditions (3) v dda = 3.6 v v in+ = 0 v v in- = v refint t a = 25 c 0 1.5 10 mv/1000 h i comp1 current consumption (4) 4. comparator consumption only. internal reference voltage not included. - - 160 260 na table 60. comparator 2 characteristics symbol parameter conditions min typ max (1) unit v dda analog supply voltage - 1.65 - 3.6 v v in comparator 2 input voltage range - 0 - v dda v t start comparator startup time fast mode - 15 20 s slow mode - 20 25 t d slow propagation delay (2) in slow mode 1.65 v v dda 2.7 v - 1.8 3.5 2.7 v v dda 3.6 v - 2.5 6 t d fast propagation delay (2) in fast mode 1.65 v v dda 2.7 v - 0.8 2 2.7 v v dda 3.6 v - 1.2 4 v offset comparator offset error (3) - 4 20 mv dthreshold/ dt threshold voltage temperature coefficient v dda = 3.3v t a = 0 to 50 c v- =v refint , 3/4 v refint , 1/2 v refint , 1/4 v refint . -15 30 ppm /c docid027973 rev 4 86/115 stm32l011x3/4 electrical characteristics 92 6.3.18 timer characteristics tim timer characteristics the parameters given in the table 61 are guaranteed by design. refer to section 6.3.13: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). i comp2 current consumption (4) fast mode - 3.5 5 a slow mode - 0.5 2 1. guaranteed by characterization results, not tested in production. 2. the delay is characterized for 100 mv input step with 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 3. in tssop14 package, where v dda pin is shared with v dd pin, i/o toggling should be minimized to reach the values given in the above table. i/o toggl ing with loaded i/o pins can generate ripple on v dd /v dda and degrade the comparator performance. 4. comparator consumption only. internal reference voltage (necessary for comparator operation) is not included. table 60. comparator 2 characteristics (continued) symbol parameter conditions min typ max (1) unit table 61. timx (1) characteristics 1. timx is used as a general term to refer to the tim2 and tim21 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1-t timxclk f timxclk = 32 mhz 31.25 - ns f ext timer external clock frequency on ch1 to ch4 0f timxclk /2 mhz f timxclk = 32 mhz 0 16 mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected (timer?s prescaler disabled) - 1 65536 t timxclk f timxclk = 32 mhz 0.0312 2048 s t max_count maximum possible count - - 65536 65536 t timxclk f timxclk = 32 mhz - 134.2 s electrical characteristics stm32l011x3/4 87/115 docid027973 rev 4 6.3.19 communications interfaces i 2 c interface characteristics the i 2 c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm) : with a bit rate up to 100 kbit/s ? fast-mode (fm) : with a bit rate up to 400 kbit/s ? fast-mode plus (fm+) : with a bit rate up to 1 mbit/s. the i 2 c timing requirements are guaranteed by design when the i 2 c peripheral is properly configured (refer to the reference manual for details) and when the i2cclk frequency is greater than the minimum given in table 63 . the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not "true" open-drain. when configured as open-drain, the pmos connected between the i/o pin and vddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement (refer to section 6.3.13: i/o po rt characteristics for the i2c i/os characteristics). all i 2 c sda and scl i/os embed an analog filter (see table 62 for the analog filter characteristics). table 62. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 100 (3) 3. spikes with widths above t af(max) are not filtered ns table 63. i2c frequency in all i2c modes symbol parameter c ondition min unit f i2cclk i2c clock frequency standard-mode 2 mhz fast-mode 8 fast-mode plus analog filter on, dnf = 0 18 analog filter off, dnf = 1 16 docid027973 rev 4 88/115 stm32l011x3/4 electrical characteristics 92 usart/lpuart characteristics the parameters given in the following table are guaranteed by design. table 64. usart/lpuart characteristics symbol parameter conditions typ max unit t wuusart wakeup time needed to calculate the maximum usart/lpuart baudrate allowing to wake up from stop mode stop mode with main regulator in run mode, range 2 or 3 -8.7 s stop mode with main regulator in run mode, range 1 -8.1 stop mode with main regulator in low-power mode, range 2 or 3 -12 stop mode with main regulator in low-power mode, range 1 -11.4 electrical characteristics stm32l011x3/4 89/115 docid027973 rev 4 spi characteristics unless otherwise specified, th e parameters given in the following tables are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions su mmarized in table 18 . refer to section 6.3.12: i/o current injection char acteristics for more details on the input/output alternate function char acteristics (nss, sck, mosi, miso). table 65. spi characteristics in voltage range 1 (1) symbol parameter cond itions min typ max unit f sck 1/t c(sck) spi clock frequency master mode -- 16 mhz slave mode receiver 16 slave mode transmitter 1.71 docid027973 rev 4 92/115 stm32l011x3/4 electrical characteristics 92 figure 31. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. figure 32. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 package information stm32l011x3/4 93/115 docid027973 rev 4 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at http://www.st.com . ecopack ? is an st trademark. 7.1 lqfp32 package information figure 33. lqfp32, 7 x 7 mm, 32-pin low-profile quad flat package outline 1. drawing is not to scale. $ $ $ % % % ! , , + ! ! ! c b ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % # 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # 7 @ . & @ 7 e docid027973 rev 4 94/115 stm32l011x3/4 package information 112 figure 34. lqfp32 recommended footprint 1. dimensions are expr essed in millimeters. table 68. lqfp32, 7 x 7 mm, 32-pin low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.100 - - 0.0039 a - - 1.600 - - 0.0630 6 ? & 0 ? 6 package information stm32l011x3/4 95/115 docid027973 rev 4 lqfp32 device marking the following figure gives an example of tops ide marking versus pin 1 position identifier location. figure 35. example of lqfp32 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 h y l v l r q f r g h 6 7 0 / 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < : : 3 l q l q g h q w l i l h u . 7 5 docid027973 rev 4 96/115 stm32l011x3/4 package information 112 7.2 ufqfpn32 package information figure 36. ufqfpn32, 5 x 5 mm, 32-pin package outline 1. drawing is not to scale. table 69. ufqfpn32, 5 x 5 mm, 32-pin package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.200 - - 0.0079 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 d2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e 4.900 5.000 5.100 0.1929 0.1969 0.2008 e2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 ! " ? - % ? 6 3 , 1 , g h q w l i l h u 6 ( $ 7 , 1 * 3 / $ 1 ( & & g g g $ $ $ h e ' e ( / h ( ( ' / ' package information stm32l011x3/4 97/115 docid027973 rev 4 figure 37. ufqfpn32 recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of tops ide marking versus pin 1 position identifier location. figure 38. example of ufqfpn32 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. $ % b ) 3 b 9 / . 0 6 y 9 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q 3 l q l q g h q w l i l h u ' d w h f r g h < : : 5 docid027973 rev 4 98/115 stm32l011x3/4 package information 112 7.3 wlcsp25 pac kage information figure 39. wlcsp25 - 25-ball, 2.133 x 2.07 0 mm, 0.4 mm pitch wafe r level chip scale package outline 1. drawing is not to scale. table 70. wlcsp25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) - 0.025 - - 0.0010 - b (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 2.098 2.133 2.168 0.0826 0.0840 0.0854 e 2.035 2.070 2.105 0.0801 0.0815 0.0829 e - 0.400 - - 0.0157 - e1 - 1.600 - - 0.0630 - e2 - 1.600 - - 0.0630 - f - 0.2665 - - 0.0105 - : / & 6 3 b $ 0 b 0 ( b 9 $ r u l h q w d w l r q u h i h u h q f h : d i h u e d f n v l g h ' h w d l o $ u r w d w h g ? 6 h d w l q j s o d q h $ % x p s e 6 l g h y l h z $ $ ' h w d l o $ h ) * h h $ e d o o o r f d w l r q h % x p s v l g h h h h = ( $ $ = ; < = f f f g g g ? e e d o o v = d d d [ e e e = package information stm32l011x3/4 99/115 docid027973 rev 4 figure 40. wlcsp25 - 25-ball, 2.133 x 2.07 0 mm, 0.4 mm pitch wafe r level chip scale package recommended footprint g - 0.235 - - 0.0093 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. back side coating. 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. table 71. wlcsp25 recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 mm dpad 0.225 mm dsm 0.290 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.250 mm stencil thickness 0.100 mm table 70. wlcsp25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) : / & 6 3 b $ 0 b ) 3 b 9 ' s d g ' v p docid027973 rev 4 100/115 stm32l011x3/4 package information 112 device marking the following figure gives an example of topside marking versus ball a1 position identifier location. figure 41. example of wlcsp25 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. / < : : 0 6 y 9 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < h d u z h h n % d o o $ l g h q w l i l h u 5 h y l v l r q f r g h 5 package information stm32l011x3/4 101/115 docid027973 rev 4 7.4 ufqfpn28 4 x 4 mm package information figure 42. ufqpn28, 4 x 4 mm, 28-pin package outline 1. drawing is not to scale. ! " ? - % ? 6 ' ( ' ( ' h w d l o = ' h w d l o < ' table 72. ufqpn28, 4 x 4 mm, 28-pin package mechanical data (1) symbol millimeters inches min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 - 0.000 0.050 - 0.0000 0.0020 d 3.900 4.000 4.100 0.1535 0.1575 0.1614 d1 2.900 3.000 3.100 0.1142 0.1181 0.1220 e 3.900 4.000 4.100 0.1535 0.1575 0.1614 e1 2.900 3.000 3.100 0.1142 0.1181 0.1220 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 l1 0.250 0.350 0.450 0.0098 0.0138 0.0177 t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - 1. values in inches are converted fr om mm and rounded to 4 decimal digits. docid027973 rev 4 102/115 stm32l011x3/4 package information 112 figure 43. ufqfpn28 recommended footprint 1. dimensions are expr essed in millimeters. ufqfpn28 device marking the following figure gives an example of tops ide marking versus pin 1 position identifier location. figure 44. example of ufqfpn28 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. ! " ? & 0 ? 6 0 6 y 9 : : 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h 3 l q l q g h q w l i l h u < 5 / * package information stm32l011x3/4 103/115 docid027973 rev 4 7.5 ufqfpn20 package information figure 45. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 1. drawing is not to scale. ! ! ? - % ? 6 $ e b e % ! ! d d d , , ! , , $ % 4 / 0 6 ) % 7 3 ) $ % 6 ) % 7 " / 4 4 / - 6 ) % 7 0 i n , docid027973 rev 4 104/115 stm32l011x3/4 package information 112 figure 46. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint 1. dimensions are expr essed in millimeters. table 73. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.152 - - 0.060 - d - 3.000 - - 0.1181 - e - 3.000 - - 0.1181 - l1 0.500 0.550 0.600 0.0197 0.0217 0.0236 l2 0.300 0.350 0.400 0.0118 0.0138 0.0157 l3 - 0.375 - - 0.0148 - l4 - 0.200 - - 0.0079 - l5 - 0.150 - - 0.0059 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.050 - - 0.0020 ! ! ? & 0 ? 6 package information stm32l011x3/4 105/115 docid027973 rev 4 ufqfpn20 device marking the following figure gives an example of tops ide marking versus pin 1 position identifier location. figure 47. example of ufqfpn20 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h 3 l q l q g h q w l i l h u < : : / ) 5 docid027973 rev 4 106/115 stm32l011x3/4 package information 112 7.6 tssop20 package information figure 48.tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. table 74. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 d 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 4.300 4.400 4.500 0.1693 0.1732 0.1772 e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - z z d z s? ? > ? l > ^ d / e ' w > e ' h ' w > e x?? uu w / e / e d / & / d / k e package information stm32l011x3/4 107/115 docid027973 rev 4 figure 49. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4. 4 mm, 0.65 mm pitch, package footprint 1. dimensions are expr essed in millimeters. k 0 - 8 0 - 8 aaa - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to four decimal digits. table 74. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 9 ! ? & 0 ? 6 docid027973 rev 4 108/115 stm32l011x3/4 package information 112 device marking the following figure gives an example of tops ide marking versus pin 1 position identifier location. figure 50. example of tssop20 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 3 l q l q g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h 3 u r g x f w l g h q w l i l f d w l r q / ) 3 < : : 5 package information stm32l011x3/4 109/115 docid027973 rev 4 7.7 tssop14 package information figure 51.tssop14 ? 14-lead thin shrink sm all outline, 5.0 x 4.4 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. table 75. tssop14 ? 14-lead thin shrink sm all outline, 5.0 x 4.4 mm, 0.65 mm pitch, package mechanical data symbol millimeters inches min typ max min typ max a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 cp - - 0.100 - - 0.0039 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 e - 0.650 - - 0.0256 - e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 4.300 4.400 4.500 0.1693 0.1732 0.1772 l 0.500 0.600 0.750 0.0197 0.0236 0.0295 l1 - 1.000 - - 0.0394 - a0 -80 -8 2 ? - % ? 6 & 3 f / ( ( ' $ $ d h e $ / docid027973 rev 4 110/115 stm32l011x3/4 package information 112 tssop14 device marking the following figure gives an example of tops ide marking versus pin 1 position identifier location. figure 52. example of tssop14 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 7.8 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 0 6 y 9 3 l q l q g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h 3 u r g x f w l g h q w l i l f d w l r q / ' 3 < : : 5 package information stm32l011x3/4 111/115 docid027973 rev 4 figure 53. thermal resistance 1. the above curves are valid for range 3. 7.8.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 76. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp32 - 7 x 7 mm / 0.8 mm pitch 60 c/w thermal resistance junction-ambient ufqfpn32 - 5 x 5 mm / 0.5 mm pitch 39 thermal resistance junction-ambient wlcsp25 - 2.133 x 2.070 mm, 0.4 mm pitch 70 thermal resistance junction-ambient ufqfpn28 - 4 x 4 mm, 0.5 mm pitch 97 thermal resistance junction-ambient ufqfpn20 - 3 x 3 mm, 0.5 mm pitch 102 thermal resistance junction-ambient tssop20 - 169 mils 74 thermal resistance junction-ambient tssop14 - 169 mils 95 0 6 y 9 7 h p s h u d w x u h ? & 3 ' p : 7 6 6 2 3 : / & 6 3 8 ) 4 ) 3 1 8 ) 4 ) 3 1 8 ) 4 ) 1 7 6 6 2 3 / 4 ) 3 docid027973 rev 4 112/115 stm32l011x3/4 part numbering 112 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 77. stm32l011x3/4 ordering information scheme example: stm32 l 011 k 4 t 6 d xxx device family stm32 = arm-based 32-bit microcontroller product type l = low power device subfamily 011 = access line pin count k = 32 pins g = 28 pins e = 25 pins f = 20 pins d = 14 pins flash memory size 3 = 8 kbytes 4 = 16 kbytes package t = lqfp u = ufqfpn y = wlcsp p = tssop temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c 3 = industrial temperature range, ?40 to 125 c options no character = v dd range: 1.8 to 3.6 v and bor enabled d = v dd range: 1.65 to 3.6 v and bor disabled packing tr = tape and reel no character = tray or tube revision history stm32l011x3/4 113/115 docid027973 rev 4 9 revision history table 78. document revision history date revision changes 07-dec-2015 1 initial release. 11-feb-2016 2 features : modified current consumption in run mode, cortex ? -m0+ core frequency range and total number of timers. updated adc conversion consumption on cover page. updated ufqfpn28 pinout: figure 6: stm32l011x3/4 ufqfpn28 pinout and table 13: pin definitions . updated table 55: rain max for fadc = 16 mhz . modified ts_cal2 description in table 57: temperature sensor calibration values . 18-mar-2016 3 changed minimum comparator supply voltage to 1.65 v on cover page. added baudrate allowing to wake up the mcu from stop mode in section 3.15.3: low-power universal asynchronous receiver transmitter (lpuart) . added number of fast and standard channels in section 3.10: analog-to-digital converter (adc) . updated table 16: current characteristics to add the total output current for stm32l011gxux. changed v dda minimum value to 1.65 v.in ta ble 18 : general operating conditions . updated table 26: current consumption in sleep mode , table 27: current consumption in low-power run mode , table 28: current consumption in low-power sleep mode and table 30: typical and maximum current consumptions in standby mode . section 6.3.15: 12-bit adc characteristics : ? table 54: adc characteristics : distinction made between v dda for fast and standard channels; added note 1. updated condition for f trig measurement. added note 4. related to r adc and removed measurement condition. updated t s and t conv . ? updated equation 1 description. ? updated table 55: rain max for fadc = 16 mhz for f adc = 16 mhz and distinction made between fast and standard channels. ? updated measurement condition in table 56: adc accuracy . added table 64: usart/lpuart characteristics . docid027973 rev 4 114/115 stm32l011x3/4 revision history 114 20-jun-2016 4 updated: ? features in cover page: stop mode values, channels? number of dma controller, i/os? number, number of peripherals communication interface. ? table 27: current consumption in low-power run mode , table 28: current consumption in low-power sleep mode , table 34: low-power mode wakeup timings , table 36: low-speed external user clock characteristics table 78. document revision history date revision changes stm32l011x3/4 115/115 docid027973 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved |
Price & Availability of STM32L011K3
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |